This paper presents a reflection and crosstalk canceling continuous-time linear equalizer (CTLE) for high-speed DDR SDRAM interface. To enhance the voltage margin in noisy multi-drop DDR SDRAM channel, the proposed CTLE cancels reflection noise by common-mode compensation and compensates crosstalk by limiting RC filter charging to overcome inversion of common-mode information. The reflection and crosstalk canceling CTLE is implemented in a DRAM process and improves the average voltage margin of 16GB RDIMM at 3.2Gbps with 28.3mV.

The advance of DRAM manufacturing technology slows down, whereas the density and performance needs of DRAM continue to increase. This desire has motivated the industry to explore emerging Non-Volatile Memory (e.g., 3D XPoint) and the high-density DRAM (e.g., Managed DRAM Solution). Since such memory technologies increase the density at the cost of longer latency, lower bandwidth, or both, it is essential to use them with fast memory (e.g., conventional DRAM) to which hot pages are transferred at runtime. Nonetheless, we observe that page transfers to fast memory often block memory channels from servicing memory requests from applications for a long period. This in turn significantly increases the high-percentile response time of latency-sensitive applications. In this paper, we propose a high-density managed DRAM architecture, dubbed 3D-XPath for applications demanding both low latency and high capacity for memory. 3D-XPath DRAM stacks conventional DRAM dies with high-density DRAM dies explored in this paper and connects these DRAM dies with 3D-XPath. Especially, 3D-XPath allows unused memory channels to service memory requests from applications when primary channels supposed to handle the memory requests are blocked by page transfers at given moments, considerably increasing the high-percentile response time. This can also improve the throughput of applications frequently copying memory blocks between kernel and user memory spaces. Our evaluation shows that 3D-XPath DRAM decreases high-percentile response time of latency-sensitive applications by ~30% while improving the throughput of an I/O-intensive applications by ~39%, compared with DRAM without 3D-XPath.

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm $^{2}$ die area.

A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open drain I/O interface, and data rate increase from 1.6 to 3.2Gb/s. To achieve high performance at low supply voltage and reduce power consumption, this work introduces new functions and describes their implementation. Data bus inversion (DBI) is employed for high-speed transactions to reduce power consumption of I/O and SSN noise. Dual-error detection, which adopts cyclic redundancy check (CRC) for DQ, and command address (CA) parity is designed to guarantee reliable transmission. GDDR5 memory also has DBI and CRC functions [1], but in this work, these schemes are implemented in a way that reduces area overhead and timing penalty. Besides these error-check functions, an enhanced gain buffer and a PVT-tolerant fetch scheme improve basic receiving ability. To meet the output jitter requirements of DDR4 SDRAM, the type of delay line for DLL is selected at initial stage according to data rate.

Three circuit techniques for a 1.5 V, 512 Mb graphic DDR4 (GDDR4) SDRAM using a 90-nm DRAM process have been developed. First, a dual-clock system increases clocking accuracy and expands internal timing margins for harmonious core operation regardless of external clock frequency. Second, a four- phase data input strobe scheme helps to increase the input data valid window. Third, a fully analog delay-locked loop which provides a stable I/O clock and has- 31.67 ps peak-to-peak jitter characteristics is designed. On the basis of these circuit techniques, the data rate is 3.2 Gbps/pin, which corresponds to 12.8 GBps in x32 GDDR4-based I/O. Also, a multidivided architecture consisting of four independent 128 Mb core arrays is designed to reduce power line and output noise.

A 1.5V, 512 Mbit GDDR4 SDRAM using a 90-nm DRAM process has been developed. The data rate is 3.2 Gbps/pin, which corresponds to 12.8 GBps in x32 GDDR4 based I/O. A multi-divided architecture consisting of 4 independent 128 Mb core arrays is designed to reduce power and output noise. Also, a dual-clock system, 4 phase data input strobe scheme and 4 phase fully analog DLL are used to increase internal timing margins.

This paper describes a CMOS implementation of a fractional-N frequency synthesizer adopting a new frequency divider and a new simplified 3-stage MASH (multistage noise shaping) delta-sigma modulator. All functional blocks, except for the low-pass filter (LPF), are integrated on a chip. A simple frequency divider architecture with a digital comparator and a 'modulus mapping circuit' in a delta-sigma modulator is suggested for a lower hardware complexity and less power consumption. The proposed fractional-N frequency synthesizer shows a rapid switching time of 2.8 mus at a 60-MHz frequency step with inherent high reference frequency and a wide loop bandwidth. The tuning range of the voltage-controlled oscillator (VCO) is 1.6similar to2.1 GHz in the measured results. The measured VCO phase noise is as low as -110.27 dBc/Hz at a 600-kHz offset and -122.99 dBc/Hz at a 7.5-MHz offset. The measured fractional spur level is -101.6 dBc. The total power consumption is 20.2 mW with a 2.5 V single power supply. The synthesizer is implemented in a 0.25-mum standard CMOS process (1-poly, 5-metal) and occupies an active area of 760 x 1280 mum.