In this paper, we propose a novel variant of the Hill cipher based on vector spaces.In the classical Hill cipher, a non-singular matrix is used for encryption but it is well known that this cipher is vulnerable to the known-plaintext attack.In our proposed cryptosystem, we eradicate this problem by encrypting each plaintext block with a new invertible key matrix.This makes our scheme immune to all existing attacks in literature on this type of ciphers and so the resulting cipher can be used as other state-of-art block cipher.To generate the invertible matrices which serve as the dynamic keys, we make use of the vector spaces along with randomly generated basis and non-singular linear transformation.In addition to this, we also study the computational complexity of the proposed cryptosystem and compare this with the computational complexities of other schemes based on Hill cipher.

Scaling of MOSFET is an important part of semiconductor industry and manufacturing of ICs and due to the scaling several issues like mobility degradation and reduction in Ion/Ioff ratio arises. To overcome these problems many structural approaches evolved over the time such as SOI, FDSOI, and multi-gate technology. Also, in this paper N-MOS Strained Si/relaxed Si0.7 Ge0.3 heterostructure is modelled and simulated using TCAD. Performance analysis of Strained-Si N-MOSFET has been done in 2D TCAD simulator. The performance of strained silicon is enhanced and analyzed using proper doping, higher work function, and thin high k dielectric oxide layer. The performance of the strained Si simulated device showed better results than the previous studied work.

In this paper; we propose DMDG-GDOV TFET device structure for low leakage current. Considering the potential benefits of DMDG-TFET, emphasize with Gate Drain Overlap (GDOV) has been simulated with high-k (HfO2) and low-k (SiO2) which results in elevated ON current (ION) as well as less leakage current. The gate region and drain region overlap shows low leakage current as compared to non-overlap gate terminal on drain side in DMDG-TFET. This gate-region on drain-region overlap reduces the electric field in the ambipolar condition and exhausts the carrier in the drain terminal side away from the junction. However, gate electrode overlapped on drain side inevitably enhances the gate-to drain capacitance (CGD) i.e. Miller Capacitance due to increase in overlap capacitance (COV) and inversion capacitance (Cinv). Hence by using high-k dielectric and low-k dielectric deposition over channel region and source-drain region respectively with dual-metal gate technique, the CGD capacitances has been reduced. This CGD further reduces the intrinsic delay by adjusting the gate metal work function of dual metal where ФTgate is (4.3 eV) greater than ФSgate (4.1 eV).

In this work a hybrid doped p type MOSFET is proposed. The structure has two gates, a main gate (MG) and a side gate (SG). The main gate controls channel conductivity of the transistor similar to the conventional MOSFET gate electrode while the side gate induces substrate doping electrically. In the proposed structure source region is doped conventionally whereas doping of the drain region is controlled electrically by varying voltage at the SG. A zero or negative voltage on the SG induces a p-type drain region underneath it. Further, doping level of the region can also be controlled by varying SG work function and its length. An optimum value for the SG work function is selected to provide the maximum I ON /l OFF current ratio. We have observed reduced peak electrical on the drain-channel junction which improves various short channel effects in the proposed device. The 2D calibrated simulation reveals that the threshold voltage (V TH ) roll-off, drain induced barrier lowering (DIBL), subthreshold slope (SS) and I ON /I OFF ratio are significantly improved in comparison to the conventional SOI MOSFET. These effects are simulated along with their conventional device counterpart.

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

In this paper, we propose a novel nano scale SOI MOSFET with hybrid doping. In the proposed device, the source of the transistor is conventionally doped while drain doping is controlled electrically by changing voltage level at an additional gate (SG) on one side of the main gate (MG). When a positive voltage at the side gate is applied, the device acts as a NMOS transistor. The hybrid doped NMOS is compared with a conventional SOI NMOS. As the drain is electrically induced, electrical field is reduced at drain junction. A 2D simulation study of the proposed device has been performed. The simulation study has shown that the proposed device has better short channel control as compared to the conventional SOI MOSFET.

In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).

Nowadays, scene text recognition has become an important emerging area of research in the field of image processing.In image processing, character recognition boosts the complexity in the area of Artificial Intelligence.Character recognition is not easy for computer programs in comparison to humans.In the broad spectrum of things, it may consider that recognizing patterns is the only thing which humans can do well and computers cannot.There are many reasons including various sources of variability, hypothesis and absence of hard-and-fast rules that define the appearance of a visual character.Hence; there is an unavoidable requirement for heuristic deduction of rules from different samples.This review highlights the superiority of artificial neural networks, a popular area of Artificial Intelligence, over various other available methods like fuzzy logic and genetic algorithm.In this paper, two methods are listed for character recognitionoffline and online.The -Offline‖ methods include Feature Extraction, Clustering, and Pattern Matching.Artificial neural networks use the static image properties.The online methods are divided into two methods, k-NN classifier and direction based algorithm.Thus, the scale of techniques available for scene text recognition deserves an admiration.This review gives a detail survey of use of artificial neural network in scene text recognition.

In this work, we propose and simulate a novel structure of a double gate metal source/ drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (V-OH) and low logic level (V-OL) as similar to VDD and similar to ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and I-ON/I-OFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors. (C) 2015 Elsevier Ltd. All rights reserved.

In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel combination of NMOS and PMOS transistors in a conventional transmission gate. The proposed device is compact, has reduced number of regions, junctions and interconnects in comparison to the conventional transmission gate.

Background: Adverse drug reactions (ADRs) are major worldwide public health problem. Proper reporting of an ADR is very important as it reduces number of deaths due to ADR and extra financial burden on patients. The aim of the study was to assess the pattern of ADR reporting in outpatients and inpatients of medicine department and to assess their causality, severity and preventability. Methods: This was a prospective observational study done from April 2013 to June 2014 or in 100 consecutive study subjects (which ever happen first) with ADRs in department of medicine. The clinical pattern, spectrum of ADRs reported and assessment of ADRs in terms of causality, severity and preventability .The causality, severity and preventability assessment was done on the basis of applying various scales for each of them. Results: A total of 153 suspected ADRs were reported and evaluated from 100 patients. Dermatological system (28%) was most commonly involved. Drug class most commonly associated was Antimicrobials (51%). 68% ADRs were classified as “Probable” in view of causality, while 68% were found to be “Moderate” in case of severity. In 65% of the cases the ADRs was “Probably Preventable”. In majority of the cases the suspected drug was withdrawn and alternate therapy was instituted. Most patients recovered from the ADR.70% of these ADR was Type A. Conclusions: Awareness about ADR reporting is still poor amongst healthcare professionals in India. Conducting regular training programmes can improve the number of ADR reporting.

In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel combination of NMOS and PMOS transistors in a conventional transmission gate. The proposed device is compact, has reduced number of regions, junctions and interconnects in comparison to the conventional transmission gate. A two dimensional (2D) calibrated simulation study has shown a reduction of 10.42% in average delay and 18.7% in the total power dissipation in the proposed transmission gate in comparison to the conventional Schottky barrier MOSFETs based transmission gate. Furthermore, it has been observed that such a transmission gate action cannot be realised by folding the conventional NMOS and PMOS transistors.

Dual Metal (DM) work function gate overlapped on drain with high-k dielectric and low-k dielectric Double Gate (DG)-Tunnel Field Effect Transistor (TFET) has been proposed for getting high ON current as well as reduced ambipolar current. This device structure has high-k (HfO2) gate dielectric which deposits on the channel region and low-k (SiO2) dielectric deposits over the source and the drain side region. The high-k dielectric at the channel region enhances the ON current and low-k dielectric of DMDG-TFET gives higher I-ON/I-OFF ratio, low off current and steep subthreshold slope than conventional DMDG-TFET. The gate-drain overlap has shown low ambipolar current as compared to the gate electrode aligned with channel-drain junction. The gate on drain overlap limits the electric field in the ambipolar condition and depletes carrier on the drain side away from the junction. This results in decreased tunnelling injection or probability. The optimized DMDG-TFET with hetero-dielectric shows higher ON-current than SiO2-only DMDG-TFET leading to a 3 orders of magnitude and getting steep average subthreshold slope of 23 mV/decade. The ambipolar current reduces 8 orders of magnitude for the 30 nm gate on drain overlapped DMDG-TFET device by choosing appropriate dual metal workfunction 4.3 eV (T-gate) and 4.1 eV (S-gate).

This paper presents the analytical potential modeling of Double Gate (DG) Tunnel Field Effect Transistor (TFET) at 50 nm channel length. In this model approach the channel potential is sum of a long channel potential and a short channel perturbation along with the whole structure rather than just the Si/SiO2 interface or the channel centre. For the validation of our analytical modeling approach we compared our result with reported data which verify our proposed design.

In this paper, we propose analytical modeling of double gate (DG) tunnel field effect transistor (TFET) which is derived by using Evanescent-mode analysis approach. This approach considers the channel potential as the sum of a long channel potential and a short channel perturbation along with the whole structure rather than just the \(\hbox {Si}/\hbox {SiO}_{2}\) interface or the channel centre. Due to this, the characteristic length lambda \((\lambda )\) does not depend on the transverse position within the channel. Analytical potential modeling of DG-TFET along with evaluation of electric field and drain current has been carried out. It has also been shown in the results that the proposed model has better channel potential and tunnel current than single-gate SOI TFET.