Critical Dimension Uniformity (CDU) is probably one of the most important process control parameters for poly gate printing process. As the design rule has been shrunk to below 100nm node and k1 approaching 0.35, the required specifications for CDU are more stringently tightened. For low k1 lithography, optical proximity effect can severely impact CDU of the critical features from different neighboring environments, such as, isolated versus dense regions, or near the crowded corners and intersections, etc. Conventional model OPC has been assumed to correct mask feature CD at a best process setting condition. The approach has been widely adopted but it is increasingly becoming less satisfactory since this method does not take into account the process variation within the acceptable process window. In ASML's LithoCruiser(TM), for a selected CD cut-line, we use a Monte Carlo approach to randomly generate process conditions within the process window to simulate thousands of CD's. Based on the predicted CD distribution, we can calculate the predicted CDU Yield within the process window. Using LithoCruiser's Application Programming Interface (API), we can set up an optimization loop to adjust mask feature snippets (or fragments) for a desired imaging and process condition to achieve user specified CDU yield. Depending on the neighboring environment, mask snippets with the same target CD may need different biases and so are the features with different target CDs due to different degrees of optical proximity effects. In Figure 1, a simplified example is used to illustrate how the approach of automatic adjustment of mask snippets achieve desired CDU yield. Figure I(a) represents a small portion of a mask layer with three different cut-lines on the same feature and (b) represents the mask portion after adjustment of each of the snippetized portion of the mask layer. (Snippet marks are in light green.). Figure 1 (c) & (d) represent the corresponding CDU yield for the selected three cut-lines before and after automatic bias correction applied to the mask.

We devised an OPC technology roadmap (Table 1) embodied in a corresponding test reticle (code named RTP4) as a benchmark for the reticle manufacturing industry. This reticle includes the polysilicon gate layer of four large ASIC-style microprocessor chips, representing four design rule generations: 0.25 micrometer, 0.20 micrometer, 0.18 micrometer, and 0.14 micrometer. In this report we summarize the challenges experienced during the building of this reticle, beginning with the scaling of scattering bar and serif OPC features according to exposure wavelength and numerical aperture. CAD data handling issues such as overall pattern complexity and choice of grid size are discussed. Three out of four RTP4 reticles made by Photronics (all written by a MEBES 4500 tool) were shown to have acceptable pattern quality. Successful die-to-database inspections for all four primary chips on one of the RTP4 reticles were performed by Applied-Orbot using their RT-8000 and RT-8000-ES systems. We also offer an initial look at the performance of this OPC technology on printed wafers with 0.18 micrometer and 0.14 micrometer line features.