With EUV lithography on the ITRS roadmap for sub-2X half-pitch patterning, it has become increasingly essential to ramp up efforts in being able to manufacture defect-free reticles or at least ones with minimal defects initially. For this purpose, much of the focus in recent years has been in finding ways to adequately detect, characterize, and reduce defects on both EUV blanks and patterned masks. For detection purposes, the current high-resolution DUV or e-beam inspection platforms are being extended to inspect EUV blanks and patterned masks but being non-actinic, make it very challenging to assess the real impact of the detected defects on EUV plane. Even with the realization of the EUV beta AIMS (TM) aerial-image based metrology in 2014-2015, the exact nature of each critical defect needs to be determined in order to be able to come up with an appropriate repair strategy. In this paper, we demonstrate the application of computational techniques to non-actinic supplemental metrology data collected on EUV mask defects to effectively determine the nature and also predict printability of these defects.The fundamental EUV simulation engine used in this approach is the EUV Defect Printability Simulator (DPS), which uses simulation and modeling methods designed specifically for the individual EUV mask components, and achieves runtimes several orders of magnitude faster than rigorous FDTD and RCWA methods while maintaining adequate accuracy. The EUV DPS simulator is then coupled with supplemental inspection and metrology measurements of real defects to effectively predict wafer printability of these defects. Several sources of such supplementary data are explored here, and may sometimes be dependent on the actual nature of defect. These sources include AFM height-profile data, SEM top-down images, and 193nm high-NA inspection images of single or multiple focus plane capture. From each of these supplemental data sources, the mask pattern and defect information is first extracted or recovered, and then forward-simulated in DPS to generate EUV aerial images subsequently analyzed for wafer printability.Each of the data sources have their strengths and limitations vis-a-vis use in a production pilot line. We exploit a mix-and-match approach to effectively filter down to the defects that really matter. The 193nm inspection image data are readily available and although the pixel-sizes are somewhat coarse compared with the mask pattern widths, computationally predicting EUV printability off these images provides a quick filter of the obvious false and nuisance defects. SEM images on the other hand provide a much better two-dimensional top-down resolution of the patterns and hence work well for full-height excess or missing absorber defects but not so well for three-dimensional defects such as pits and bumps in the EUV multilayer or foreign material defects such as contamination. AFM height profile measurements generally provide the best available resolution on three-dimensional defects and thereby are well-suited for further simulations to EUV, however, AFM tip and image stability, and data acquisition time need to be comprehended.Computationally exploiting these supplemental defect inspection and metrology data in this mix-and-match approach effectively filters defects down to those that really matter on printed wafer. We see this approach as being vital to getting comprehensive defect learnings during the EUV pilot phase implementation and delivering well-characterized EUV masks to the wafer fab at substantially lower cost-of-ownership.

As optical lithography continues to extend into sub-0.35 k1 regime, mask defect inspection and subsequent review has become tremendously challenging, and indeed the largest component to mask manufacturing cost. The routine use of various resolution enhancement techniques (RET) have resulted in complex mask patterns, which together with the need to detect even smaller defects due to higher MEEFs, now requires an inspection engineer to use combination of inspection modes. This is achieved in 193nm AeraTM mask inspection systems wherein masks are not only inspected at their scanner equivalent aerial exposure conditions, but also at higher Numerical Aperture resolution, and special reflected-light, and single-die contamination modes, providing better coverage over all available patterns, and defect types. Once the required defects are detected by the inspection system, comprehensively reviewing and dispositioning each defect then becomes the Achilles heel of the overall mask inspection process. Traditionally, defects have been reviewed manually by an operator, which makes the process error-prone especially given the low-contrast in the convoluted aerial images. Such manual review also limits the quality and quantity of classifications in terms of the different types of characterization and number of defects that can practically be reviewed by a person. In some ways, such manual classification limits the capability of the inspection tool itself from being setup to detect smaller defects since it often results in many more defects that need to be then manually reviewed. Paper 8681-109 at SPIE Advanced Lithography 2013 discussed an innovative approach to actinic mask defect review using computational technology, and focused on Die-to-Die transmitted aerial and high-resolution inspections. In this approach, every defect is characterized in two different ways, viz., quantitatively in terms of its print impact on wafer, and qualitatively in terms of its nature and origin in the mask manufacturing process. The latter characterization qualifies real defect signatures, such as pin-dots or pin-holes, extrusions or intrusions, assist-feature or dummy-fill defects, writeerrors or un-repairable defects, chrome-on-shifter or missing chrome-from-shifter defects, particles, etc., and also false defect signatures, such as those due to inspection tool registration or image alignment, interlace artifacts, CCD camera artifacts, optical shimmer, focus errors, etc. Such qualitative characterization of defects has enabled better inspection tool SPC and process defect control in the mask shop. In this paper, the same computational approach to defect review has been extended to contamination style defect inspections, including Die-to-Die reflected, and non Die-to-Die or single-die inspections. In addition to the computational methods used for transmitted aerial images, defects detected in die-to-die reflected light mode are analyzed based on special defect and background coloring in reflected-light, and other characteristics to determine the exact type and severity. For those detected in the non Die-to-Die mode, only defect images are available from the inspection tool. Without a reference, i.e., defect-free image, it is often difficult to determine the true nature or impact of the defect in question. Using a combination of inspection-tool modeling and image inversion techniques, Luminescent’s LAIPHTM system generates an accurate reference image, and then proceeds with automated defect characterization as if the images were simply from a die-to-die inspection. The disposition of contamination style defects this way, filters out >90% of false and nuisance defects that otherwise would have been manually reviewed or measured on AIMSTM. Such computational defect review, unifying defect disposition across all available inspection modes, has been imperative to ensuring no yield losses due to errors in operator defect classification on one hand, and on the other, has enhanced defect characterization and detection capability of the inspection platform itself notwithstanding the number of defects detected in the process.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The limitation of 1.35 NA posed by water-based lithography has led to the application of various resolution enhancement techniques (RET), for example, use of strong phase-shifting masks, aggressive OPC and sub-resolution assist features, customized illuminators, etc. The adoption of these RET techniques combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for a mask inspection engineer. Inspecting masks under their actinic-aerial image conditions would detect defects that are more likely to print under those exposure conditions. However, this also makes reviewing such defects in their low-contrast aerial images very challenging. On the other hand, inspecting masks under higher resolution inspection optics would allow for better viewing of defects post-inspection. However, such inspections generally would also detect many more defects, including printable and nuisance, thereby making it difficult to judge which are of real concern for printability on wafer. Often, an inspection engineer may choose to use Aerial and/or high resolution inspection modes depending on where in the process flow the mask is and the specific device-layer characteristics of the mask. Hence, a comprehensive approach is needed in handling defects both post-aerial and post-high resolution inspections. This analysis system is designed for the Applied Materials Aera (TM) mask inspection platform, all data reported was collected using the Aera.In this paper, we propose the use of a novel computational approach to reviewing defects post actinic-inspections. For aerial-images, this involves first determining whether the defect is real, nuisance, or false based on user-specified print CD error criteria. The defect print criteria can be different at different critical locations within the same image, enabled by use of Luminescent's image-based topology markers. Real and nuisance defects are then characterized based on their type and origin, for example, isolated pin-dot or pin-hole, extrusion or intrusion, assist-feature or dummy-fill defect, write-error or un-repairable defect, chrome-on-shifter or missing chrome-from-shifter defect, particle, etc. False defects are also characterized based on their origin, for example, those due to tool registration or image alignment, imaging related artifacts, thermal variation, focus issues, etc. While aerial inspection has the benefit of innate nuisance immunity, visual or manual-operator classifications of these defects in the low-contrast aerial-images is error-prone, and very laborious and time-consuming.For high resolution images, the same computational classification scheme is applied. The key difference here is that wafer printability of defects detected in high-resolution mode is computed under Aerial-image conditions using Luminescent's Lithographic Plane Review (LPR) product. In this approach, high resolution images are first inverted to mask-plane where the defective and reference mask patterns are recovered from the inspection images, and then forward-simulated to appropriate aerial-image exposure conditions. The simulated aerial defect and reference images are analyzed in the same comprehensive scheme as aerial images from the inspection tool.This computational approach to defect review post actinic mask-inspection is imperative to ensuring no yield losses due to errors in operator defect classification on one hand, and on the other, furthering the detection capability or sensitivity of the inspection platform itself notwithstanding the number of defects detected in the process.

The routine use of aggressive OPC at advanced technology nodes, i.e., 40nm and beyond, has made photomask patterns quite complex. The high-resolution inspection of such masks often result in more false and nuisance defect detections than ever before. Traditionally, each defect is manually examined and classified by the inspection operator based on defined production criteria. The significant increase in total number of detected defects has made manual classification costly and non-manufacturable. Moreover, such manual classification is also susceptible to human judgment and hence error-prone.Luminescent's Automated Defect Classification (ADC) offers a complete and systematic approach to defect disposition and classification. The ADC engine retrieves the high resolution inspection images and uses a decision-tree flow based on the same criteria human operators use to classify a given defect. Some identification mechanisms adopted by ADC to characterize defects include defect color in transmitted and reflected images, as well as background pattern criticality based on pattern topology. In addition, defect severity is computed quantitatively in terms of its size, impacted CD error, transmission error, defective residue, and contact flux error. The final classification uses a matrix decision approach to reach the final disposition. In high volume manufacturing mask production, matching rates of greater than 90% have been achieved when compared to operator defect classifications, together with run-rates of 250+ defects classified per minute. Such automated, consistent and accurate classification scheme not only allows for faster throughput in defect review operations but also enables the use of higher inspection sensitivity and success rate for advanced mask productions with aggressive OPC features.

A wafer's printed CD error can be impacted by unaccounted mask making process variation. Unaccounted mask CD and/or corner rounding alters the intended drawn mask pattern contributing to a wafer's printed CD error. During OPC wafer calibration, average mask bias and corner rounding are accounted for in the OPC model, but random local mask making process variations or mask-to-mask variations can be difficult to account in such model calibration. Thus when a wafer's CD has error, it can be difficult to determine if the general root cause was due to mask or wafer or both. An in-line monitoring application has been developed to extract accurate mask CD and rendered mask polygon from collected mask CD-SEM images. Technical information will be presented on the challenges of accurately extracting information from SEM images. In particular, discussions include SEM image calibration, contour extraction, inverse pattern rendering, and general image processing to account for mask SEM aberrations (translation, rotation, & dilation), tool-to-tool variation, vendor-to-vendor variation, run-to-run variation, and dark/bright field pattern-to-pattern variation. After accurate mask SEM contours are obtained, lithographic simulations are performed on extracted polygon contours to determine the impact of mask variation on wafer CD. This paper will present detail information about the Inverse Pattern Rendering (IPR) capabilities developed for a virtual Wafer CD (WCD) application and its results, which is proven to achieved 0.5 nm accuracy across multiple critical layers from 28 nm to 40 nm nodes on multiple CD-SEM tools over multiple mask shop locations.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns under mask inspection optical conditions continues to diminish. Furthermore, as mask complexity and MEEF has also increased, it requires detecting even smaller defects in the already narrower pitch mask patterns. This leaves the mask inspection engineer with the option to either purchase a higher resolution mask inspection tool or increase the detector sensitivity on the existing inspection system or maybe even both. In order to meet defect sensitivity requirements in critical features of sub-32nm node designs, increasing sensitivity typically results in increased nuisance (i.e., small sub-specification) defect detection by 5-20X defects making post-inspection defect review non-manufacturable.As a solution for automatically dispositioning the increased number of nuisance and real defects detected at higher inspection sensitivity, Luminescent has successfully extended Inverse Lithography Technology (ILT) and its patented level-set methods to reconstruct the defective mask from its inspection image, and then perform simulated AIMS dispositioning on the reconstructed mask. In this technique, named Lithographic Plane Review (LPR), inspection transmitted and reflected light images of the test (i.e. defect) and reference (i. e., corresponding defect-free) regions are provided to the "inversion" engine which then computes the corresponding test and reference mask patterns. An essential input to this engine is a well calibrated model incorporating inspection tool optics, mask processing and 3D effects, and also the subsequent AIMS tool optics to be able to then simulate the aerial image impact of the defects. This flow is equivalent to doing an actual AIMS tool measurement of every defect detected during mask inspection, while at the same time maintaining inspection at high enough resolution. What makes this product usable in mask volume production is the high degree of accuracy of mask defect reconstruction, predicting actual AIMS measurements to within +/-4% CD error for > 95% of defects while not missing any OOS (out-of-specification) defect and maintaining high simulation throughput of >= 250 defects/min on Luminescent's distributed computing platform. This technique enables inspection recipes to be setup based on the sensitivity required to detect small but lithographically-significant defects, even if in the process a large number of nuisance defects are detected.LPR is being implemented as an integral part of defect classification for high-volume sub-32nm technology nodes and higher. Furthermore, this technique will be essential to the lithographic disposition of defects detected on EUV masks inspected under non-actinic conditions.

Contact hole (CH) patterning for DRAM/Flash presents a key challenge for design rule below 50nm due to aggressive low-k(1) conditions common in the leading DRAM/Flash memory designs. Combining optical proximity corrections (OPC) to the mask and optimized illumination has become an important part of production-worthy lithography processes for the 65nm node. At k(1)< 0.31, both resolution and imaging contrast can become severely limited at NA < 0.85 with some commonly available off-axis illumination sources. Hyper-NA and immersion lithography with polarized illumination capability can significantly increase the process latitude and is indispensable for manufacturing at sub-50nm design rule and beyond.In this work, we describe our single-exposure approach for patterning Flash/DRAM contact-hole patterns with 120nm minimum pitch (and 60nm CH target CD). We use 6% attPSM dark-field mask both in simulations and for wafer exposures on ASML XT:1700i at NA=1.2. We begin with illumination source optimization using full vector high-NA simulation with (unpolarized and Y polarized illumination) a production resist stack and taking into account during the optimization all manufacturability requirements for the corresponding diffractive optical element (DOE) that produces the optimized source at the mask level. Using the optimized source, model-based OPC treatment was performed, which includes scattering bars (SB) placement using IML (TM) technology and model-based CH feature biasing (MOPC) to achieve the optimum pattern printing fidelity in-focus and process latitude. To further increase of the depth of focus (DOF) for common process window (CPW) from 150mn to > 250m, we used the focus scan (or, focus drilling) technique which is available in today's leading 193nm scanners.Our results showed that, for the 120nm minimum pitch Flash CH patterns used, hyper-NA (NA > 1) and immersion lithography (ASML XT:1700i platform was used in both simulation and scheduled for wafer exposures) is necessary, together with optimized illumination and model based OPC treatment, to achieve a yielding baseline process (common process window with DOF similar to 100nm). We also demonstrate that polarized illumination can significantly enhance the overall imaging performance, i.e., worst-case DOF can be increased > 25% with optimized source, which is limited by the dense pitch CH arrays for this particular Flash CH pattern. With focus scan enabled for imaging. we show that the worst-case individual DOF can be easily doubled (from 150nm to > 300nm) and EL at best focus (BF) remains > 10% even at the largest focus range settings (400nm). The common process window decreased as focus scan range was increased, indicating that to maintain optimum common process window, MOPC treatment must be also performed under the same focus scan conditions. Patterning optimization (from illumination optimization to OPC) with focus scan enabled shows excellent promise as a single-exposure solution for patterning this 45nm Flash CH pattern and beyond.For the 120nm pitch Flash CH pattern, the optimized patterning solution predicated a worst-case DOF=130nm before OPC and a common process window DOF similar to 100nm @ 6% EL using the optimized source, model based OPC (both SB and MOPC bias), using ASML XT 1700i with unpolarized illumination. With Y linear polarization, which enhances the imaging contrast for the dense pitch (all in X direction), we observed a > 20% increase in worst-case DOF compared to the unpolarized illumination, using separately optimized illumination source for each illumination mode, before OPC. Compared to the unpolarized illumination, this provides a more favorable starting condition for carrying out subsequent OPC treatment.To explore the possibility for manufacturing, focus scan was included in all process window and latitude simulations using the same optimized illumination source and OPC obtained without focus scan. We found that the worst-case DOF (in 1x2 CH arrays) increased from 130nm to 350nm as focus scan range setting was increased from 0 to 400nm, with EL near BF remained > 10% within the same focus scan range. With focus scan enabled, 1x2 CH arrays (the most isolated) is no longer the limiting factor for overall DOF performance for this Hash CH pattern. Therefore, with OPC treatment done with focus scan, we expect a common process window DOF > 250nm should be easily achievable. These latest results show great promise to our single-exposure approach to patterning the 45nm node Flash CH mask, and will be compared to the wafer results (to be reported elsewhere [7]). For wafer exposures, we'll use the same DOE decomposition technique as described earlier [1]. The mask should contain OPC treatment generated using a set of illuminators available on the scanner, when recombined they resemble closely the optimized illumination source, so that in-focus patterning and process latitude can be directly assessed from wafers exposed using the same illuminator (set).Future work includes illumination source optimization and model based OPC using focus scan, the required wafer exposures to confirm the simulation results reported for the 120nm pitch Flash CH pattern, refine simulations using the GRAIL model for more accurate comparison with the wafer results from the ASML immersion scanners. SB and MOPC treatment will be refined to meet the requirements of manufacturing under the current and future low-k(1) conditions and under optimum focus scan conditions. Also results will be compared with those from the simultaneous source and mask optimizations [13] and other alternative CH patterning techniques [14, 15].

Patterning contact-hole mask for Flash/DRAM is probably one of the most challenging tasks for design rule below 50nm due to the extreme low-k1 printing conditions common in the memory designs. When combined with optical proximity corrections (OPC) to the mask, using optimized illumination has become a viable part of the production lithography process for 65nm node. At k1<0.31, both resolution and imaging contrast can become severely limited by some of the current imaging tools with NA<0.85 and using standard illumination sources. Hyper-NA immersion lithography increases the process latitude and is therefore expected to become more indispensable for manufacturing under extreme low-k1 conditions for sub-50nm design rule. In this work, we describe our process optimization approach for patterning Flash/DRAM contact-hole patterns with 130nm, 120nm, and smaller minimum pitch design rules. Here we use 6% attPSM mask for simulation and actual exposure in ASML XT 1400i (NA=0.93) and 1700i (NA=1.2) respectively. We begin with the illumination source optimization using full vector high-NA calculation (VHNA) with production resist stack and all manufacturability requirements for the source shaping diffractive optical element (DOE) are accounted for during the source optimization. Using the optimized source, IMLTM technology based scattering bars (SB) placement together with model based OPC (MOPC) are applied to the original contact-hole design. In-focus printing and process latitude simulations are used to gauge the performance and manufacturability of the final optimized process, which includes the optimized mask, optimized source and required imaging settings. Our results show that for the 130nm pitch Flash contact-hole patterns, on ASML XT 1400i at NA=0.93, both optimized illumination source and immersion lithography are necessary in order to achieve manufacturability. The worst-case depth of focus (DOF) before SB and MOPC is 100-130nm at 6% EL, without common process window (PW) and with MOPC, the worst-case DOF is >200nm at 6% EL. The latter is in excellent agreement with the wafer results from ASML XT 1400i, and the predicated CDs match well with the measured at isolated, medium and dense pitch contact-holes to within 5nm. For the 120nm pitch Flash contact patterns, ASML XT 1700i at NA=1.2 must be used, together with optimized illumination source, to achieve the same or better process latitude (worst-case DOF at 6% EL), and for the Flash pattern used, further enhancements of >20% in DOF @ 6% EL using Y linear polarization can be achieved, before SB and MOPC. With preliminary SB and MOPC, the worst-case DOF @ 6% EL is increased from 100nm to 150nm and with common PW for all critical CDs, from isolated to dense contact-holes. Two examples of customized polarizations are considered in the above simulations to demonstrate the effects of polarizations on imaging and process latitude for pattern specific contact-holes. The pros and cons of the current patterning solution are discussed and compared with alternatives.

The contact hole imaging is a very challenge task for the optical lithography process during IC manufacturing. Lots of RETs were proposed to improve the contrast of small opening hole. Scattering Bar (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 contact imaging. In this study, an effective model-based SB OPC based on IML technology is implemented for contact layer at 90nm, 65nm, and 45nm nodes. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. Then, we selected the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, the model-based SB OPC is performed. Next, model OPC can be applied with the presence of SB for the entire chip. It is important to note that, for patterning at k1 near 0.35 or below, it may be necessary to include 3D mask effects with a high NA OPC model. With enhanced DOF by IML and immersion process, the low k1 production worthy contact process is feasible.

Imaging contact and via layers continues to be one of the major challenges to be overcome for 65nm node lithography. Initial results of using ASML MaskTools' CPL Technology to print contact arrays through pitch have demonstrated the potential to further extend contact imaging to a k1 near 0.30. While there are advantages and disadvantages for any potential RET, the benefits of not having to solve the phase assignment problem (which can lead to unresolvable phase conflicts), of it being a single reticle - single exposure technique, and its application to multiple layers within a device (clear field and dark field) make CPL an attractive, cost effective solution to low k1 imaging. However, real semiconductor circuit designs consist of much more than regular arrays of contact holes and a method to define the CPL reticle design for a full chip circuit pattern is required in order for this technique to be feasible in volume manufacturing. Interference Mapping Lithography (IML) is a novel approach for defining optimum reticle patterns based on the imaging conditions that will be used when the wafer is exposed. Figure 1 shows an interference map for an isolated contact simulated using ASML /1150 settings of 0.75NA and 0.92/0.72/30deg Quasar illumination. This technique provides a model-based approach for placing all types features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary (COG), attenuated phase shifting mask (attPSM), alternating aperture phase shifting mask (altPSM), and CPL. In this work, we investigate the application of IML to generate CPL reticle designs for random contact patterns that are typical for 65nm node logic devices. We examine the critical issues related to using CPL with Interference Mapping Lithography including controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, and reticle manufacturing constraints. Multiple methods for deriving the interference map used to define reticle patterns for various RET's will be discussed. CPL reticle designs that were created from implementing automated algorithms for contact pattern decomposition using MaskWeaver will also be presented.

The theory of interference mapping lithography (IML) is presented for low k1 (k1<0.4) contact hole imaging. IML with a coherent source is shown to be analogous to methods used in creating a Fresnel lens. With IML for a partially coherent source, the interference map is calculated by using the first eigenfunction of the transmission cross coefficient (TCC). From this interference map, clear 0° AFs and for clear 180° AFs are placed in the optimal location. Thus, IML is a method to place AFs via a model. From the interference map, a method for creating a CPL mask is demonstrated. Using IML, techniques to optimize a binary mask or a CPL mask are presented for maximizing the exposure latitude (EL) or depth of focus (DOF). These techniques are verified with simulation. Using IML for maximum EL, a CPL mask with 100nm (k1=0.39) contacts was created and exposed on an ASML /1100 ArF scanner using NA of 0.75 and Quasar illumination (σin=0.72, σout=0.92, span angle=20°). Measurements on the exposed wafers show that IML CPL results in printing 100nm contacts through pitch (200nm minimum pitch to isolated) with 0.45μm DOF at 10% EL.

Double Dipole Lithography (DDLä) has been demonstrated to be capable of patterning complex 2D devices patterns. [1,2,3] Due to inherently high aerial image contrast from dipole illumination, we have found that it can meet lithography manufacturing requirements, such as line edge roughness (LER), and critical dimension uniformity (CDU), for the upcoming 65nm node using ArF binary chrome masks. For patterning at k1 below 0.35, DDL is one of the promising resolution enhancement techniques (RET), which can offer process latitudes that are comparable to more costly alternatives such as two-exposure alternating PSM. To use DDL for printing actual IC devices, the original design data must be converted into a "vertical (V)" mask and a "horizontal (H)" mask for the respective X-dipole and Y-dipole exposures. We demonstrated that our model-based DDL mask data processing methodology is capable of converting complex 2D logic and memory designs into dipole-compatible mask layouts. [2,3] Due to the double exposure, stray light must be well controlled to ensure uniform printing across the entire chip. One intuitive solution to minimize stray light is to apply large patches of chrome in the open field areas in order to reduce the background (non-pattern area) exposure level. Unfortunately, this is not viable for a clear-field poly gate mask as it incorporates a positive photoresist process. We developed an innovative and practical background-shielding scheme called sub-resolution grating block (SGB), which is part of the DDL layout conversion method for full-chip application. This technique can effectively minimize the impact of long-range stray light on critical features during the two exposures. Reticles inspection is another important issue for the implementation of DDL technology. In this work, we reported a methodology on how to characterize defects and optimize inspection sensitivity for DDL RET reticles.

For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k1 for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k1 values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k1, it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPLTM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IMLTM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RET's including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Resolution Enhancement Techniques (RET), or low k1 imaging, has been deployed successfully to extend the resolution limits of optical lithography significantly below half-λ for today's poly gate mask in the state-of-the-art manufacturing processes. However, achieving satisfactory contact hole patterning through the full pitch range required for the 90nm and 65nm technology nodes has greatly challenged the leading process development effort. Currently, attenuated PSM's with transmission between 5% and 9% are used to enhance the resolution of dark field contact hole patterns. Using conventional illumination with a low sigma, which is the common method employed for att-PSM, limits the minimum pitch that can be resolved on the wafer. By using off-axis illumination (OAI) it is possible to image smaller pitches. However, the same attributes that enhance imaging for dense patterns severely degrade the imaging of isolated patterns. Using Chromeless Phase Lithography (CPL), sub-wavelength isolated contact patterns can be imaged using strong off-axis illumination, such as Quasar, dipole and double dipole, etc. By applying modeled sub-resolution and non-printing features, we found it is possible to achieve very high-resolution contact imaging with exceptional process latitude. Both phase shifted and non-phase shifted patterns can be much larger than sub-resolution assist features (or anti-Scattering Bars) used on dark field binary reticles (~three times larger), making the reticle pattern easier to manufacture. Using this method, sub-wavelength bright patterns on a dark field can be imaged through the full pitch range. We have shown that it is feasible to push the contact resolution limit to 0.33 k1 or smaller.

Chromeless Phase Lithography (CPL) with a high NA exposure tool is shown to be an attractive technology solution for the 65nm node [1]. Under strong image enhancement conditions, the traditional definition of minimum defect printability specifications is no longer adequate. This paper investigates defect printability issues for CPL technology. Based on optimized scattering bar OPC treatments through pitch, a set of defect printability quantification (DPQ) patterns was designed. In the DPQ design, a number of defect types have been programmed with progressively increasing defect size from 0.05(lambda/NA) to 0.3(lambda/NA). Each defect type and size on the actual CPL reticle were then fully characterized using an advanced CD SEM metrology system, the KLA8450R(TM) with both wafer and reticle capabilities. This is a very critical step for quantifying defect printability, since in order to accurately assess the printability, the defect dimension must be well correlated to the original DPQ design on the reticle. The DPQ reticle was then printed using a high numerical aperture (NA) scanner (ASML/850(TM)) so that it is possible to characterize the defect printability for each of the programmed defects and the impact on CD through pitch. Minimum printable defect (MPD), maximum non-printable defect (MNPD), and critical dimension (CD) variation percentage were used as metrics to characterize the critical defect size and the sensitivity of each defect type. The purpose of this study is to understand the tolerance of the CLM technology to printable defects and establish a realistic and sensible defect specification.

For cost-effective Integrated Circuit (IC) manufacturing, it is highly desirable to use Binary-Chrome Masks (BIMs) instead of Phase Shifting Masks (PSMs). For the 70nm technology node, it is of particularly appealing if Argon Fluoride (ArF) BIMs can still be used. In this paper, we demonstrate that double dipole ArF exposure together with BIMs is capable of achieving acceptable overlapped process window for printing 70nm Critical Dimension (CD) features. The main challenge of using such a technique for IC manufacturing is how to properly decompose the original mask patterns into two separate orientation masks (vertical and horizontal). To compensate for the possible two-dimensional (2D) pattern distortion due to the strong proximity effect, a novel set of