In the context of aging populations, it has become necessary to develop new methods and devices for the daily home-based self-rehabilitation of elderly people. To this end, this paper proposes and evaluates the use of an easy-to-use single battery-powered device including a 3D accelerometer and a 3D gyroscope, where light algorithms, such as the complementary filter and the Kalman filter, are implemented to estimate the elbow joint angle. During experiments, a robotic arm and a human arm were used to obtain an error interval for each tested algorithm; the robotic arm allows for reproducible movements and reproducible results, which allows us to independently verify the impact of parameters such as the sensor’s movement speed on the algorithm precision. The experimental results show that the algorithm that uses only accelerometer data is one of the most relevant since it allows us to obtain a Root Mean Square Error between 1.83° and 5.52° at a sensor data rate of 100 Hz, which is similar to the results obtained using the data fusion algorithms tested. Nevertheless, it has a lower power consumption since it requires only 58 cycles when using an ARM Cortex-M4 processor (which is lower than that of the other data fusion algorithms tested by a factor of at least two), and it does not necessitate the additional sensor required by the other data fusion algorithms tested (such as a gyroscope or a magnetometer). The algorithm using only accelerometer data also seems to be the algorithm with the lowest power consumption and should be preferred. Moreover, its power consumption can be reduced by more than the increase in the error when reducing the rate of the data output by the sensor. In this work, a reduction in the data rate from 100 Hz to 10 Hz increased the RMSE by a factor of 1.8 but could reduce the power consumption associated with the sensor and the algorithm’s computation by a factor of 10. Finally, the experimental results show that the higher the speed of the sensor’s motion, the higher the error obtained using only accelerometer data. Nevertheless, the algorithm that uses only accelerometer data remains well suited to rehabilitation exercises or mobility evaluations since the speed of the sensor’s movement is also moderate.

Energy harvesting technology provides a promising alternative to batteries usage in low power systems. The integration of these solutions on the same silicon support is a real technological and technical challenge. This paper proposes a multi-harvesting fully-integrated system architecture combining AC and DC sources. Based on a MATLAB/Simulink model, the proposed system allows the calibration of an optimal solution. It is designed and simulated in 40 nm CMOS process, proving that using an AC source as second input, allows to start a harvesting system with very low DC source as main source.

The huge improvements in integrated circuits manufacturing has faced great challenges between process optimization, performance requirements and the trade-off between low power operation and reliability for long term use. Both the variability at time zero and the time variability due to external constraints and aging phenomena make mandatory the validation of the CMOS technology nodes from device to circuits and products under operation. While High-K Metal-Gate (HKMG) offered good compromises down to 28nm gate-length, the move to Fully Depleted Silicon on Insulator (FDSOI) allows to further scale the dimension down to 14nm effective gate-length with ultra-thin equivalent gate-oxide thickness (EOT) of 1.35 nm. This has been obtained guarantying a small subthreshold slope for switching, small drain-induced barrier lowering (DIBL) for limited short-channel effect (SCE) and excellent current drivability thanks to a proper gate-stack with HfO2/SiON optimization and adapted rapid thermal processing and annealing. We give new insights to determine first the performance with temperature, the process variability impact at time zero and the robustness of CMOS nodes submitted to interface traps, oxide charge and recoverable traps. Their role is analysed using accelerated DC and AC experiments in devices to SRAM cell and array, focusing on the balance between hot-carrier and bias temperature damage. This allows to guaranty the technology robustness, speed performance and limited power consumption for product qualification.

High buffer chains consumption is a serious impediment, particularly for low power and energy harvesting systems. In this paper, we present a novel approach named CGTx (Control Gate Transistor) for designing CMOS butter chains. We introduce two gate control transistors that separate and regulate the pull-up and pull-down transistor gates. This configuration reduces short-circuit leakage which helps to reduce total power consumption. This proposed technique is compared to the LECTOR (LEakage Control TransistOR) technique and conventional inverter gate in terms of leakage power during switching for a single inverter gate and total power consumption for a chain of six inverters. The total consumption for a chain of six inverters with high drive capacitance using CGTx inverters is 4% lower compared to conventional inverters and 28% lower compared to LECTOR technique.

An ultra low power acoustic wake-up detector based on high frequency signal analysis is presented in this paper. Focused on environmental or military Internet of Things (IoT) applications, it aims at detecting in real time the presence of specific animal species or drones for generating alerts and for triggering power consuming tasks such as high frequency signal recording only when needed.This wake-up detector continuously monitors the presence of specific frequencies in an analog acoustic signal, with a good frequency selectivity and a high frequency range detection capability. It is based on an ultra-low power analog frequency to voltage converter using a current-mirror, analog timers and synchronous comparators.Dedicated to long term stealth environmental or military surveys, a strong emphasis has been put on power consumption reduction in order to reduce batteries constraints. Its power consumption has been reduced to 2.5µW, leading to an autonomy of more than 28 years with a single coin cell CR2032 battery.

Within an increasingly connected world, the exponential growth in the deployment of Internet of Things (IoT) applications presents a significant challenge in power and data transfer optimisation. Currently, the maximization of Radio Frequency (RF) system power gain depends on the design of efficient, commercial chips, and on the integration of these chips by using complex RF simulations to verify bespoke configurations. However, even if a standard 50Ω transmitter’s chip has an efficiency of 90%, the overall power efficiency of the RF system can be reduced by 10% if coupled with a standard antenna of 72Ω. Hence, it is necessary for scalable IoT networks to have optimal RF system design for every transceiver: for example, impedance mismatching between a transmitter’s antenna and chip leads to a significant reduction of the corresponding RF system’s overall power efficiency. This work presents a versatile design framework, based on well-known theoretical methods (i.e., transducer gain, power wave approach, transmission line theory), for the optimal design in terms of power delivered to a load of a typical RF system, which consists of an antenna, a matching network, a load (e.g., integrated circuit) and transmission lines which connect all these parts. The aim of this design framework is not only to reduce the computational effort needed for the design and prototyping of power efficient RF systems, but also to increase the accuracy of the analysis, based on the explanatory analysis within our design framework. Simulated and measured results verify the accuracy of this proposed design framework over a 0–4 GHz spectrum. Finally, a case study based on the design of an RF system for Bluetooth applications demonstrates the benefits of this RF design framework.

The voltage feedback operational amplifier (VFOA) and the current feedback operational amplifier (CFOA) are the main voltage type output opamps currently used in electronics. The VFOA is a combination of an operational transconductance amplifier (OTA) used as an input stage and an output voltage buffer (VB). In this paper, the CFOA is described as a combination of an operational transconductance conveyor (OTC) used as an input stage and with an output voltage buffer. Two similar CMOS architectures are then defined, analysed and simulated in order to provide some elements of comparison. Results, from a typical CMOS 0.35μm transistor parameters, show the role of compensation capacitances in boosting the frequency performances of the non-inverting amplifier.

Extended Drain MOS (EDMOS) transistors were studied about hot-carrier (HC) degradation and its involvement in hard breakdown (BD) events as these smart power devices represent a big challenge to optimize under Off/On mode switching in RF circuits. N-channel devices with gate-length L G =0.5µm and two gate-oxide thicknesses were tested Tox= 2.3nm (GO1) and 8.5nm (GO2). The sensitivity to BD between Off-mode and HC is pointed out in GO1 through the hot-hole injections (HHI) that are involved as a function of gate-voltage V GS = V TH and V Gmax where the V TH case induces HC damage that can be used with series resistance increase (ΔR SD ) to detect BD events in the drift region. Hole trapping and interface traps are generated leading to the dominant effect of HHI, with very close generation rates between Off- and On- mode stressing. This can be used to prevent circuit aging giving warning level for confidence in AC lifetime for power amplifiers class E and class A.

This paper presents a smart embedded Functional Electrical Stimulator (FES), able to stimulate a muscle only when a specific movement pattern occurs. This pattern is detected using an inertial measurement unit (IMU) coupled with a feature detector and a neural classifier. Architecture of the FES is first presented, then embedded processing algorithms composed of feature extraction and neural network classification are detailed. Results show that the muscle vibration happening when stimulation is needed can be recognized in more than 90% of cases using less than 3% of average embedded processor resources on a ARM M4F.

P- and N- channel Extended Drain MOSFETs (EDMOS) are analyzed through its sensitivity to Hot-Carrier (HC) degradation using accelerated lifetime technique. N- and P- channel EDMOS are optimized for a gate-length L-G = 0.5 mu m, with gate-oxide thickness at 2.3 nm. We have evaluated more precisely the HC damage caused from channel to the extended drain by an improved extraction of series resistance (Delta R-SD) till a 2nd order mobility modeling as a function of stressing V-GS from V-GS = 0 to V-Gmax. This allows to determine the worst-case of lifetime dependence in relation to the damage in the drift zone where breakdown sensitivity is found to be intimately bound up with the hot-hole (HH) injection efficiency in N-EDMOS while P-EDMOS exhibits a larger security margin.

Being used in for environmental and military Internet of Things (IoT), a low power wake-up system based on frequency analysis is presented in this paper. It aims at detecting continuously the presence of specific very high frequencies in the input acoustic signal of an embedded system. This can be used for detecting specific animal species, and for triggering a recording system or generating alerts. Used for harmful species detection, this helps to save harvests or to protect strict nature reserves. It can also be used for detecting the presence of drones in a specific restricted area. This acoustic low power wake-up system uses a simple 16 bits micro-controller (MCU), with a strong emphasis on the low power management of the system, having a target of continuous detection for at least one year on a single standard 1.2Ah - 12V lead battery. For that, it makes the most of mixed analog and digital low power MCU modules. They are including comparators, timers and a special one present on Microchip MCU, called Charge Time Measurement Unit (CTMU). This is a driven constant current source for making time to frequency conversions at a very low power and algorithmic cost. Optimizing low power modes, this low power wake-up system based on frequency analysis has a power consumption of 0:56mW, leading to approximately 3 years of battery life on a single standard 1:2Ah - 12V lead cell.

An ultra low power acoustic wake-up detector based on high frequency signal analysis is presented in this paper. Focused on environmental or military Internet of Things (IoT) applications, it aims at detecting in real time the presence of specific animal species or drones for generating alerts and for triggering power consuming tasks such as high frequency signal recording only when needed. This wake-up detector continuously monitors the presence of specific frequencies in an analog acoustic signal, with a good frequency selectivity and a high frequency detection capability. It is based on an ultra-low analog frequency to voltage converter using a current-mirror, analog timers and comparators. Dedicated to long term stealth environmental or military surveys, a strong emphasis has been put on power consumption reduction in order to limit size and weight of the system. This power consumption has been reduced to 34μW, leading to a full year of autonomy including the microphone when powered by 3 coin cell CR2032 batteries.

Being used for synchronizing and triggering environmental and military Internet of Things (IoT) wireless networks, an ultra low power wake-up system based on frequency analysis is presented in this paper. With an average power consumption of 34μW, this wake-up detector is able to detect signals in different frequency bands, generating a separate output interrupt for each of them. Adding an additional frequency band detector only costs an additional 500nA. Applications to data retrieval in a military smart dust using a drone on a battlefield, and for activation and synchronization of a environmental wireless sensor network are presented. This later uses a multi-frequency light pulses burst propagation algorithm for triggering a whole wireless sensor network in harsh conditions such as a dense rain forest in 50ms, and for synchronizing it with a timing precision of less than 20μs in a large network.

This paper presents a radio frequency (RF) measurement method that allows to determine electrical characteristics such as scattering parameters or impedance of contactless passive chips, using common measurement devices such as oscilloscope, personal computer, and directional coupler. The measurements obtained using this method are as accurate as those obtained with vector network analyzer (VNA) measurements, while providing several improvements. First, the method makes it possible to measure a chip's impedance in activation state, which requires large input power, not compatible with VNA measurements. Second, this method realizes a real-time measurement, which consists in impedance measurement as a function of time. Therefore, this real-time measurement makes it possible to detect and measure the impedance changes of an actual contactless smart card's integrated circuit during a load modulation communication at different powers. Finally, this real-time impedance measurement gives important information on chips' electrical characteristics that can be used to optimize near-field communication devices design in order to reduce the power losses within an RF identification tag.

Dans le cadre de la formation à l'ISEN Toulon, les étudiants de première année de Master ont pour mission de réaliser un projet sur une durée de 300h. Ce projet a eu pour vocation première la réalisation d'un produit en utilisant les outils d'aide à la simulation proposés par le CNFM, mais également les outils de gestion de projets. Dans ce cadre, les étudiants encadrés par des enseignants-chercheurs de différents sites (ISEN Toulon, Polytech'Marseille, le Laboratoire IM2NP, l'EMSE), ont développé une source aléatoire intégrée faible consommation. La conception a été réalisée par les étudiants sur le site de l'ISEN Toulon et Polytech Marseille et les tests sécuritaires ont été effectués sur le site de l'Ecole des Mines de Saint Etienne, à Gardanne. Ce projet multi site est une réelle plus-value pour les étudiants comme pour les encadrants.

We use dedicated test structures for high performance low power (LP) CMOS nodes designed with 28nm FDSOI and 28nm LP devices. These allow to distinguish AC high frequency dependence as a function of high temperature (125°C) experiments for Bias Temperature Instability (BTI) and Hot-Carrier Damage (HCD) (1) for inverter chains (buffers) and logic gates in order to obtain AC-DC ratios (2) in standard logic gate paths for timing degradation with activity as a variable. This shows that NBTI remains the worst-case of damage at high temperature with a frequency independence due to the limited effect of relaxation with activity lowering (t on /t off ) while HCD still represents a significant damage contribution at lower temperature due to the frequency and pulse shape dependences during transients. An accurate quantitative analysis is checked in a data path example with ELDO simulations that distinguishes each contribution.

This paper presents a study on the effect of Forward Body Biasing on the laser fault sensitivity of a CMOS 90nm microcontroller. Tests were performed on a register of this target, under several supply voltage and body bias settings, showing significant laser sensitivity variations. Based on these results, a method which aims at decreasing fault repeatability by using variable supply voltage and body bias settings is proposed. Finally, tests are performed on an implementation of this method on a temporally redundant AES and the results are presented.

In this paper we present the behavior of a single nonvolatile Flash floating gate memory cell when it is irradiated, from the backside, by femtosecond laser pulses. For the first time we show that the memory cell state can change using this type of stimulation. The measurements were carried out with an experimental setup with an ad hoc probe station built around the optical bench. We present the experimental results using different memory bias conditions to highlight the charge injection in the floating gate. Then, we study the cell degradation to check the state of the tunnel oxide and the drain-bulk junction. The aim is to understand the failure mechanisms and use this technique for accelerated reliability tests. Finally we report the experimental results achieved for different laser energies.

-This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on a PMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of PMOS transistor. It reveals the possible activation of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.