All elements required for writing, storing, and reading information in a bubble lattice device have been designed and fabricated in a single test chip. Design considerations and operating margins are given for the five major components of the device: (1) write station (nucleation and wall state control in an isolated-bubble region); (2) read station (wall state discrimination and bubble detection in an isolated-bubble region); (3) storage (confinement and translation of a close-packed hexagonal bubble lattice); (4) isolated-bubble to bubble lattice transition; and (5) bubble lattice to isolated-bubble transition. All functions have been demonstrated on a single test device operating in a data-in, data-out mode. Initial error rates and sources of errors are discussed.

The use of a regular array, or lattice, of magnetic bubbles for the storage of information requires two kinds of functions: the read-write functions involving the generation and discrimination of bubbles with different wall structures, and the access functions involving the insertion and removal of bubbles at selected locations in the lattice. In a column-accessed bubble lattice device, accessing is accomplished by first translating the lattice to position the desired column of bubbles in an input-output access channel and then translating this column along the channel to a detector area outside of the lattice while simultaneously introducing new bubbles from a generator area at the other end of the channel. An analysis of the influence of device design parameters on access rate indicates that the most important parameters are the column translation rate and lattice capacity. A device is described that was designed to study the translation of a lattice of bubbles and of a single column of bubbles within the lattice. Quasistatic operating margins and dynamic measurements of this test device indicate that the column-access configuration provides feasible means for the rapid access of bubbles from a lattice.

A new approach to bubble memories, called a bubble lattice file (BLF), is described. This approach employs a periodic bubble lattice to define bit positions while the information is contained in the wall structure of the bubbles. The principal advantage of the BLF is the increased storage density, sixteenfold when the resolution capability of the fabrication process is the limiting factor. The device functions required for the BLF, including accessing and write/read operation, are described. Significant differences between BLF and the T‐I bar bubble memories are discussed.

One of the primary functions required for a bubble lattice device is the translation of the lattice for accessing information. This paper describes the results of a test device designed to study the translation of a bubble lattice. The design utilizes buffer regions at each end of the lattice. The buffer regions contain parallel stripe domains aligned along the direction in which the stripe domains aligned along the direction in which the lattice is translated. The lattice initialization procedure involves first applying an a.c. in‐plane field to form an array of parallel stripe domains. The stripe domains are then cut into bubble domains by conductor lines fabricated on the bubble material. The domains within the active area of the device are isolated from the domains in the surrounding area by selectively ion milling the garnet material. A 12 column X 28 row lattice was quasistatically translated by applying bipolar current pulses to pairs of conductor lines placed so as to provide a driving force on every fourth column of bubbles in the lattice. Using a 2.5 Oe peak, 1 MHz bias modulating field to minimize coercivity effects the minimum current required to translate the lattice was 3 mA which corresponds to a power dissipation in the condutor lines of 165 nW/bubble. The bias field operating margin at 3.5 mA was 10.5 Oe±25%.

A 1024-bit bubble memory chip having a storage density of 1.5 × 106bits/in2has been designed, fabricated, and tested. The chip organization consists of two identical, independent, 512-bit major-minor-loop configurations. All device functions have been operated at the chip level at 500 kHz. The bubble chip has been mounted in a ceramic module assembly containing a sense amplifier chip, the in-plane...

This paper describes the fabrication and operation of a 52‐bit bubble domain memory chip designed to test the concept of on‐chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble. All other functions are performed by a permalloy overlay driven by an external rotating field. The metallurgy consists of 200 Å evaporated permalloy for magnetoresistive sensors. 4000 Å electroplated permalloy for propagation etc., and 6000 Å electroplated copper for control lines.

LPE magnetic garnet films are now being grown with magnetic defect densities less than 10/cm2and with a high degree of reproducibility. Attention is now being directed toward developing optimum garnet film compositions for specific device applications. The europium-yttrium garnet system has been found to be suitable for 1-5µm diameter bubbles, has a low temperature sensitivity, and may be used for devices operating at frequencies up to 500 KHZ.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter Facebook Reddit LinkedIn Tools Icon Tools Reprints and Permissions Cite Icon Cite Search Site Citation V. Sadagopan, M. Hatzakis, K. Y. Ahn, T. S. Plaskett, L. L. Rosier; HIGH‐DENSITY BUBBLE DOMAIN SHIFT REGISTER. AIP Conf. Proc. 1 March 1972; 5 (1): 215–219. https://doi.org/10.1063/1.3699425 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentAIP Publishing PortfolioAIP Conference Proceedings Search Advanced Search |Citation Search

The design of a memory consisting of NDRO shift register loops, generators, input and output decoders (all implemented with bubble domain devices) and magnetoresistive detectors will be discussed. The feasibility of the individual components has been demonstrated.

Measurements of domain-wall velocity, using the ``bubble collapse'' technique, in Y3GaxFe5−xO12 crystals with 1.0 ≤x≤1.7 show that the usual ``viscous'' damping model of domain-wall motion does not apply. At fields less than about 1 Oe above the threshold H0, the wall mobilities are greater than 103 cm/sec Oe. A few oersteds above the threshold, the field dependence of the wall velocities changes abruptly and, at higher fields, the velocities depend linearly on (H-H0)1/2.

Garnet compositions have been developed which utilize stress-induced uniaxial anisotropy to attain stable magnetic bubble domains. The compositions were designed to be useful as epitaxial films on single crystal Gd3Ga5O12 or Sm3Ga5O12 substrates and were tested as annealed (> 1200°C) bulk crystal platelets which were mechanically stressed by being bonded to glass substrates with thermal setting epoxy resins at ∼ 200°C. These annealed platelets exhibited cubic domains prior to mechanical stressing and were free of any growth anisotropy. Properties of (Sm,Dy,Y)3(Fe,Ga)5O12 and (Gd,Y,Yb)3(Fe,Ga)5O12 garnets relevant to bubble domains are discussed.

Orthoferrite single crystal growth in PbO-PbF2 and Pb0-PbF2-B2O3 fluxed melts has been studied with particular attention being given to crystal morphology and perfection. Dendritic structures and bands (striae) were observed and are discussed in terms of possible {110} and {001} crystal growth modes. Optically visible bands are associated with variations in the lead impurity but not with the silicon impurity which is constant throughout these crystals. These bands impede bubble domain motion selectively, according to the relative band and domain wall orientations, but not as seriously as grain boundaries or twins. On the basis of these considerations, the effects of bands can be minimized by selecting crystal platelets grown in a {001} mode when the net magnetization is oriented 〈001〉.

The design considerations for a semiconductor crosspoint consisting of an SCR-diode-resistor circuit are presented and the fabrication process is briefly reviewed. These crosspoints have an ON-resistance of three to four ohms and a capacitance of approximately three picofarads. They can be interconnected on ceramic modules to form matrix arrays for use in telephone line switching applications.

A new device has been used to study the surface recombination velocity and surface state characteristics of Si-SiO 2 interfaces. The device consists of an epitaxially-formed junction diode. When the junction is forward-biased, minority carriers are injected from the heavily-doped substrate into the lightly-doped epitaxial region. The thickness of the epitaxial region is much less than the diffusion length for minority carriers. Thus, the diode current for a given junction forward bias is directly proportional to surface recombination velocity at the Si-SioO 2 interface. A gate electrode over the SiO 2 has been included to vary surface potential. Thus, this new device permits one to simultaneously study MOS capacitance-voltage characteristics as well as surface recombination velocity. The capacitance-voltage characterics indicate the surface states exhibit a quasi-continuous energy distribution. N-type surfaces exhibited donor levels lying in the range of ∼0.15 to ∼0.45 eV above the valence band; their density was found to vary from ∼5 × 1012to 5 × 1013states/cm2/eV. In contrast, p-type surfaces exhibited acceptor levels lying in the range of ∼0.15 to ∼0.45 eV below the conduction band; their density was comparable to those observed on n-type surfaces. The maximum value of surface recombination velocity was found to vary from 3 × 103to > 104cm/s. Surface recombination velocity was found to correlate directly with surface state density.