Summary form only given. GaAs/AlGaAs quantum well, 850 nm vertical-cavity surface-emitting lasers (VCSELs) with lateral current injection and shallow implanted apertures were fabricated. The device performance was characterized using small-signal and large-signal analysis, power-current-voltage measurements, and optical spectra measurements.

We relate the optical beam waist of a vertical-cavity surface-emitting laser (VCSEL) to a measurement of the transverse mode splitting found in the device's optical output spectra and to a measurement of beam divergence, We show experimentally that the results are in good agreement. Accurate knowledge of beam waists is useful for tailoring devices for single-mode or for high-speed operation and to better understand and interpret the mode spectrum.

Results are presented on a lateral current injection vertical cavity surface emitting laser (VCSEL) structure, the implant apertured, index guided VCSEL (I2-VCSEL). This approach was previously used for 980 nm emission and has now been adapted for 850 nm emission. The threshold current is as low as 0.8 mA for 7μm diameter current apertures. Typical slope efficiencies of 0.45–0.5 mA/mW are obtained for output mirror reflectivity of 99.5%. Small-signal measurements of the modulation response indicate instrument-limited bandwidths in excess of 11 GHz. Large-signal measurements demonstrate 10 Gb/s operation with bit-error rates below 10−13. In addition, high repetition rate pulses were generated by gain switching both single and multimode VCSELs. These Gaussian pulses had time bandwidth products below 2.5, pulse widths as low as 29.6 ps and timing jitter as low as 5.5 ps.

A dry etch process for patterning SiO2/TiO2 distributed Bragg reflectors (DBRs) for vertical-cavity surface-emitting lasers was demonstrated. The etching was conducted using an inductively coupled plasma (ICP) system. Both SF6/Ar and Cl-2/Ar based etching chemistries were investigated. Very slow etch rates were obtained for TiO2 when using a Cl-2/Ar chemistry due to the low volatility of the etch products, TiClx. Using an SF6/Ar based chemistry, similar etch rates for TiO2 and SiO2 were obtained, which is desired for etching through the alternating SiO2 and TiO2 layers of the DBR. An average etch rate of 1200 Angstrom /min was achieved at ICP and radio frequency (rf) powers of 500 and 250W, respectively. Wet chemical etch processing was also explored using a buffered oxide etchant (BOE) and diluted HF. Etch rates of similar to 2050 Angstrom /min and similar to2.7 mum/min were obtained for BOE and HF:H2O (1:3), respectively. However, a significant etch-undercut of the DBR structure and delamination at the SiO2/TiO2 interfaces, due to internal stress created between these layers, were observed when these wet etchants were used. (C) 2001 The Electrochemical Society. All rights reserved.

We characterize the small-signal frequency response of intracavity contacted /spl sim/970 nm VCSEL's designed for flip-chip bonding to electronic circuits and then modified with reduced capacitance and a novel lateral current injection method to obtain a high-speed response. We measure 3-dB bandwidths in excess of 10 GHz and an extracted K-factor limited f-max of 95 GHz for fabricated single-mode /spl sim/970-nm lasers.

We show that two-photon photocurrent imaging can be used to nondestructively study vertical cavity surface emitting lasers on a microscopic level. In particular, we study the aperture isolation created by shallow ion implantation. The combination of two-photon backside imaging and a probe station is ideal for internal and full wafer characterization. The required peak and average power levels for testing can be easily satisfied by available compact ultrafast laser sources, making the technique practical and user friendly.

We present a detailed theoretical study on the optical and L–I characteristics of implant-apertured index-guided vertical-cavity surface-emitting lasers. Our theory is based on a beam propagation method combined with thermal, gain, and rate-equation models. Spatial hole burning and modal competition are taken into account. Our results are in excellent agreement with the experimental data and show the effect of the current aperture size (determined by the ion implant) on the modal performance of these devices. In particular, the current-aperture size can be fixed independently from the index-guide size to obtain minimum threshold, single-mode operation.

We have fabricated vertical-cavity surface-emitting lasers (VCSELs) which, for the first time, effectively combine a shallow ion implanted aperture, for current confinement under a thin highly conducting lateral current injection layer, and an independent index guide for optical beam confinement (I/sup 2/-VCSELs). Both features are possible only because they are made before a top dielectric mirror is deposited and patterned, and are photolithographically defined for improved size reproducibility compared to oxide-confined designs. The devices emit near 980 nm and have optical power outputs of 1 mW at 2.5-mA input. The 12-VCSEL design also easily incorporates coplanar contacts allowing us to operate flip-chip bonded I/sup 2/-VCSEL's on silicon test chips at data rates of nearly 1 Gb/s.

We report the flip-chip bonding of a 16/spl times/16 array of 970-nm vertical-cavity surface-emitting lasers (VCSELs) to an array of silicon CMOS driver circuits. The small-signal bandwidth of a flip-chip bonded VCSEL is in excess of 4 GHz. Individual VCSELs are capable of being modulated by the CMOS circuits at 1 Gb/s. The thermal impedance of the flip-chip bonded VCSELs is 1/spl deg/C/mW. The measured crosstalk suppression between channels is approximately 20 dB. Simultaneous parallel testing of up to 80 VCSELs at 1 Gb/s per VCSEL is demonstrated.

We describe the first integration of vertical-cavity surface-emitting laser arrays with gigabit-per-second CMOS circuits via flip-chip bonding.

The authors describe an optoelectronic switching chip with 1024 differential optical inputs and 1024 differential optical outputs with individual channels tested above 600 Mbit/s. The technology for the chip consists of 850 nm GaAs/AlGaAs multiquantum well (MQW) detectors and modulators, flip-chip bonded onto silicon CMOS with substrate removal to allow access to the optical devices.

We demonstrate the integration of a large (64 × 68) p-i(MQW)-n GaAs diode array to a silicon CMOS chip, using flip-chip solder bump bonding techniques together with concomitant GaAs substrate removal. The capability of removing a relatively large area of GaAs substrate cleanly and uniformly is attributed to the introduction of a new selective etch stop with a smooth isotropic etchant for the GaAs substrate removal. The presence of the lattice matched In0.49Ga0.51P selective etch stop layer has no detrimental effect on the performance of the GaAsAlGaAs optical detector/modulator diodes, which gives the chip the large IO count of 4352.

We present the first high-speed optoelectronic very large scale integrated circuit (VLSI) switching chip using LU-V optical modulators and detectors flip-chip bonded to silicon CMOS, The circuit, which consists of an array of 16 x 1 switching nodes, has 4096 optical detectors and 256 optical modulators and over 140K transistors. All but two of the 4352 multiple-quantum-well diodes generate photocurrent in response to light, Switching nodes have been tested at data rates above 400 Mb/s per channel, the delay variation across the chip is less than +/- 400 ps, and crosstalk from neighboring nodes is more than 45 dB below the desired signal, This circuit demonstrates the ability of this hybrid device technology to provide large numbers of high-speed optical I/O with complex electrical circuitry.

We have made two-beam smart-pixel optical receivers using a hybrid attachment of GaAs-AlGaAs multiple-quantum-well (MQW) pin devices to foundry-fabricated 0.8-mu m linewidth CMOS circuits. Results from a repeater in which receiver output is coupled to a transmitter circuit driving a differential pair of MQW modulators are reported. When tested with high-contrast, directly-modulated laser diodes, an optical energy of 26 fJ (-21.5 dBm) in each beam is required to obtain a bit error rate of 1 x 10(-9) at 622 Mb/s, and operation at this error rate is observed to 1 Gb/s. The described receiver (one of several we have made) has three amplification stages, with the first being of the transimpedance type. The reported receiver fits easily within a 45 x 25 mu m area, and the entire repeater circuit draws about 2 mA from a 5-V power supply, with the transmitter accounting for about 20 percent of the total.

We introduce the concept of synchronous smart-pixel optical receivers, and present the first use of a clocked-sense amplifier as a smart-pixel optical receiver, Such a receiver uses the controlled application of positive feedback to obtain low-power compact digital amplification, We describe the design and simulation of two types of optical receivers based on a clamped bit-line sense amplifier (CBLSA), and a conventional sense amplifier (CSA), Both of these circuits have been realized in 0.8 micron-linewidth foundry CMOS with hybrid-bonded GaAs-AlGaAs MQW detectors and modulators attached to the circuit, Operation in excess of 750 Mb/s is demonstrated, within a layout area of 44 mu m x 22 mu m, with a bias-dependent estimated power dissipation of 1 to 2 mW, Operation with one or two input beams is possible, with approximate minimum detected photocurrent levels at 320 Mb/s of 8 mu A (similar to 100 fJ) for single-beam operation and 2.5 mu A/beam (similar to 30 fJ/beam) for two-beam operation, all in the CBLSA-based circuit.

A two-beam optical repeater circuit operates to 1 Gb/s, consumes 10 mW, occupies about 1100 /spl mu/m/sup 2/, and is realized with a technology capable of providing thousands of optical inputs and outputs to foundry-grade VLSI silicon CMOS circuitry. The technology provides this capability by attaching GaAs/AlGaAs multiple-quantum-well (MQW) modulators and detectors to VLSI CMOS with flip-chip solder bonding. The main unique features are summarized.

We describe the parallel optical test of a photonic first-in-first-out (PFIFO) buffer memory based on flip-chip CMOS/SEED optoelectronic technology. The PFIFO detects pages of 4 by 8 binary bits, stores them in a 32 bit deep buffer memory, and transmits them in a 16 by 2 output modulator array. All 32 I/O and memory channels functioned, with an average input power of 40 microwatts and a minimum output contrast ratio of 2:1.

We present a 2-kbit, 50-Mpage/s, photonic first-in, first-out page buffer based on gallium arsenide/aluminium-gallium arsenide multiple-quantum-well diodes that are flip-chip bonded to submicrometer silicon complementary-metal-oxide-semiconductor circuits. This photonic chip provides nonvolatile storage (buffering), asynchronous-to-synchronous conversion, bandwidth smoothing, tolerance to jitter or skew, spatial format conversion, wavelength conversion, and independent flow control for the input and the output channels. It serves as an interface chip for parallel-accessed optical bit-plane data. It represents the first smart-pixel array that accomplishes the vertical integration of multiple-quantum-well modulators and detectors directly over active silicon VLSI circuits and provides over 340 transistors per optical input-output. Results from high-speed single-channel testing and real-time array operation of the photonic page buffer are reported.

In summary, an optical memory smart pixel array had been designed and fabricated. The functions and performance of this device had been tested and confirmed. We demonstrated a smart pixel capable of storing 4 pages of 32-bit memory with parallel operation of the smart pixel array at clock rates up to 277 MHz.

We describe 8/spl times/8 arrays of smart pixels, designed and fabricated using MQW modulators and detectors flip-chip-solder-bonded to silicon CMOS circuits. The individual circuits implement 2 input, 1 output embedded control switching nodes. Four arrays from two different designs were fabricated and tested. For the array with the highest yield, 60 of 64 nodes functioned correctly at low speeds and were tested up to 250 Mb/s without re-adjusting individual bias voltages with the maximum speed of an individual node of 375 Mb/s. For the second-generation array, the center 4/spl times/8 section of the array was tested at data rates beyond 700 Mb/s with individual nodes having short term bit error rates below 10-/sup 11/.