This paper investigates the avalanche robustness of high-voltage silicon PiN diodes under unclamped inductive switching (UIS) conditions. Devices were experimentally tested across a wide range of load inductances. A pronounced reduction in robustness - both in time-to-failure and in maximum avalanche current - was observed at low inductance values, deviating from previously reported monotonic trends. These results indicate the presence of an additional electrically driven failure mechanism, distinct from the classical energy-driven avalanche failure. Based on the experimental evidence and failure analysis, two complementary failure mechanisms are proposed to explain the observed behavior: (i) an energy-driven mechanism, supported by TCAD simulations, and (ii) an electrically driven mechanism, for which a working hypothesis is formulated based on prior literature.

In spite of the importance of a detailed description of the filamentary current constriction of the IGBT during the turn-off operation that could lead to the device's failure, there are to date no quantitative 3D simulation results of the filament growth and dynamic that can be compared with experimental results. In this paper we present 3D numerical simulations on the failure mode in the Unclamped Inductance Switching (UIS) test operation, extended to the full device area, which will be usefully compared with detailed experimental results on a large number of trench IGBT test samples. For the first time extended 3D dynamic electrothermal simulations of the whole die are made, to take into account both the electric and thermal effects of the filamentary conduction in avalanche mode. The onset of a filament growth condition for a current level just above the turnover voltage evaluated by the 3D simulations, and the area of the filament, obtained for the first time, are well in agreement with the quantitative data extracted by the experimental evaluations. Moreover, the thermal heating due to the filament formation is found to be quite independent from the current level, because it depends on the current density in the filament, rather than on the injected current. The delay time between the filament formation and the final failure time seen in the experimental results is verified to be due to the movement of the filament all around the chip surface in search of a cooler spot. The movement of the filament along the whole die area is verified for the first time by full area 3D electrothermal dynamic simulations, with times in agreement with the experimental delay between filament formation and final failure seen in all the failure reports.

SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO 2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Leakage current is a key reliability indicator for power semiconductor devices, as its evolution under stress directly reflects degradation mechanisms. High Temperature Reverse Bias (HTRB) testing provides a standardized procedure to monitor this parameter over prolonged operation under elevated temperature and high reverse-bias conditions. Beyond electrical degradation, the test can also reveal reliability issues associated with thermally induced mechanical stress, which may alter the epoxy mold compound package. To investigate this phenomenon, this study presents a novel approach for real-time strain monitoring of the package during HTRB. As sensor, fiber-optic technology was considered. Particularly, Fiber Bragg Grating (FBG) strain sensors were glued on a TO-247 high-voltage Silicon diode. To validate the proposed methodology, two distinct bonding configurations of the FBG sensor were evaluated. In configuration (a), the FBG is bonded along its full length using an epoxy layer, whereas in configuration (b) the fiber is attached to the package only at two discrete points. In both cases, the measured strain variations exhibit a clear correlation with the evolution of the leakage current, confirming that mechanical deformation influences the leakage current behavior under stress conditions. These results demonstrate the feasibility of using FBG-based strain monitoring to track package deformation and its coupled electro-thermal response during HTRB qualification.

In this paper, a new trench shielding concept against high electric fields is presented by means of an experimental demonstration backed up with 3D TCAD simulations. The novel concept has been applied on an advanced 3D Quasi-Planar Trench (QPT) SiC MOSFET rated at 1200 V and 50 A. The protection approach consists of two key design pillars by employing: 1) shallow trench depths embedded in deeper P-Well Channel regions which are accordingly 2) shallower than deeper highly doped P-Body regions under the source contact. This design provides a double protection scheme for enhancing the device blocking performance and shielding the gate oxide at the critical regions along the trench MOS gate structure. Three different QPT design structures were examined with varying protection levels, with each design having a consistent trench depth but varying trench dimensions across the JFET region (QPT1 with no embedded Trench in P-Well), P-body (QPT2 with partially embedded trench in P-Well), and into the N+ source region (QPT3 with fully embedded trench in P-Well). The blocking characteristics, including the off-state leakage behaviour, were analyzed for the proposed device structures. The optimized QPT structure performs showcases BV performance close to the best-in-class reference planar structure with a deviation of only ~ 0.3 %. The experimental results were further validated through advanced 3D TCAD simulations, which examined electrostatic behavior, and studied electric field distributions along different cross-sections of the trench.

This work presents a custom High Temperature Reverse Bias (HTRB) platform designed for accelerated screening of encapsulation mold compounds in power devices. The system enables parallel testing with real-time leakage current monitoring and in-situ reverse I–V acquisition under controlled temperature and humidity, allowing early detection of thermal runaway. The platform was validated on commercial 1.2 kV diodes encapsulated with two different compounds. Results show that low sodium ion concentration is more critical for long-term reliability than a high glass transition temperature. The setup can serve as a preliminary screening tool to guide compound selection before conducting time-intensive 1000-h qualification HTRB.

This article analyzes the capacitance-voltage characteristics of SiC MOSFETs under a measurement configuration where an ac signal is applied to the Gate and a dc bias is imposed on the drain. Under these conditions, an unexpected capacitance peak appears in the inversion region, whose origin is investigated by taking into account the contribution of interface traps. An analytical expression for the measured capacitance is derived using a small-signal equivalent circuit model, revealing a direct dependence of the peak on the device transconductance and drift region resistance. To support the model, a TCAD analysis is carried out in Sentaurus, focusing on the impact of varying physical and technological parameters, such as channel doping, channel length, drift doping, and trap profiles, on the capacitance peak. The results confirm that the peak is influenced by both transconductance and drift region resistance, as well as by interface traps which are primarily responsible for the observed frequency dependent behavior. These insights are relevant for understanding the dynamic performance of SiC MOSFETs and optimizing their switching behavior.

We investigate the physical and electrical characteristics of the Al-doped or undoped HfO 2 /SiO 2 gate stacks on 4H-SiC by testing MOSCAP chips fabricated in house. A clear reduction in accumulation capacitance (C ox ) with increasing chuck temperature from room temperature up to 523 K is observed, with Al-doping playing a key role and aligning with temperature-dependent Landau ferroelectric theory. Chips annealed at 1100°C in N₂ ambient show the highest C ox decrease rates while maintaining functional MOS interfaces with acceptable flatband voltage, hysteresis, and Dit profiles. TCAD simulations on a double trench MOSFET model, based on the extracted data indicate improved electro-thermal performance, demonstrating that Al-doped HfO₂/SiO₂ gate stacks are a promising approach for enhancing 4H-SiC power devices.

Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are essential in modern electronics, enabling efficient power conversion and control in a wide range of applications. Wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have been shown to boost device performance, by providing higher efficiency and faster switching for high-power, high-frequency applications. Although optimised for standard operation, their performance under short circuit (SC) events remains critical mostly because of the higher current density. Notably, SiC MOSFETs can only withstand SC conditions for a few microseconds, necessitating larger layouts or faster control electronics to prevent the catastrophic failure of the device. This paper introduces a novel power device, the Ferro-Power MOSFET, that integrates a ferroelectric material into the gate stack of a power SiC MOSFET. This innovative approach leverages the temperature-dependent dielectric constant of ferroelectrics to effectively reduce the temperature rise during short-circuit events without altering the basic layout of the device neither the control electronics. TCAD simulations and design optimisation of a 1.2 kV SiC MOSFET reveal substantial enhancements, achieving temperature and current reductions of up to 31% and 42%, respectively, without compromising current conduction during normal operation. It stands to reason that this concept is general and can be broadly applied to any power MOSFET. Moreover, it is bolstered by recent achievements in ferroelectricity in CMOS-compatible hafnium oxide (HfO2), thus prospecting concrete experimental developments in power semiconductors.

There are some technological issues in SiC MOSFETs that are still unsolved. One of the main problems is the high density of traps/defects at the SiC/SiO2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. The high-density of defects at the SiC/SiO2 interface is a relevant problem since it can influence the overall performance of the device, causing detrimental impacts on threshold voltage stability, channel mobility and leakage current amplitude. Due to the fundamental importance of the SiC/SiO2 interface characterization, several techniques have been employed to investigate defects properties related to this region. In this work non-classical C-V measurements are performed. Capacitance is measured between Gate and Source terminals while a fix DC voltage is imposed on the Drain. This latter is considered among positive values in the first case, while it is chosen as a negative voltage in the second case. The arising capacitances in both cases show an unexpected behavior which can be related to interface properties. To this aim numerical analysis is performed in Sentaurus TCAD environment.

This study investigates a cost-effective semi-Superjunction (SSJ) solution for 3.3 kV silicon carbide (SiC) MOSFETs, comparing planar and trench configurations. The semi-SJ method, utilizing side-wall implantation and silicon oxide trench refill, offers a practical alternative to the more complex multi-epitaxial growth approach. Through TCAD simulations, the planar semi-SJ MOSFET (planar-SSJ) achieved a 48 % reduction in specific on-state resistance (7.5 mΩ.cm2) and a 4.5 % improvement in maximum blocking voltage (4210 V) compared to conventional planar MOSFET. The trench semi-SJ MOSFET (trench-SSJ), depending on the deep trench angle, can further reduce the specific on-state resistance by 52 % (7.0 mΩ.cm2) and improve the maximum blocking voltage by 6 % (4285 V), while also providing a wider implantation window and a lower gate-oxide electric field.

This paper presents a novel High-Temperature Reverse Bias testing platform designed for real-time, automated monitoring of leakage current in multiple high-voltage devices under uniform stress conditions. The setup enables accelerated stress testing at elevated temperatures while ensuring thermal safety and minimizing manual intervention. A case study is conducted on two identical 1200 V silicon diodes encapsulated with different epoxy mold compounds (EMCs) to evaluate the system's screening capabilities. Experimental results show significant post-stress degradation in devices with higher sodium content including, increased leakage and reduced breakdown voltage. Additional degradation effects, such increased leakage at low voltage, are also observed. TCAD simulations reveal that localized donor-like traps at the $\text{Si} / \text{SiO}_{2}$ interface can explain the experimental findings, suggesting a failure mechanism linked to ionic contamination in the termination region. The study demonstrates the platform's effectiveness for comparative reliability screening and failure mode analysis.

In this paper we demonstrate a fully optimized process flow for silicon carbide semi-Superjunction (semi-SJ) Schottky barrier diodes, achieving high performance with readily available foundry technology. Using SF6-based etching, we fabricated 7 gm deep trenches with smooth, well-angled sidewalls (80-85) and optimized implantation of the trench bottom and sidewalls. Scanning capacitance and atomic force microscopy, combined with TCAD simulations, confirmed the successful sidew all doping implantation. The resulting structures are expected to exhibit an RDSON of 6.2 m Omega.cm(2) and a 4 kV breakdown voltage, outperforming planar diodes. These advancements enable seamless integration of semi-SJ technology into SiC power devices, paving the way for next-generation high-voltage applications.

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (RDS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in RDS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in RDS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs.

Silicon carbide (SiC) power MOSFETs are widely used in high-voltage applications for their superior electrical and thermal properties. The SiC Gate-All-Around (SGAA) structure enhances performance by eliminating termination regions and enabling high breakdown voltage and current density. However, localized heating during short-circuit events limits its robustness. This work proposes the integration of a ferroelectric layer (e.g., HfO2) into the SGAA gate stack—forming the FERRO POWER SGAA—to exploit temperaturedependent dielectric behavior and improve thermal management. TCAD simulations confirm enhanced robustness and reduced current overshoot during transient conditions.

Silicon Carbide (SiC) is a leading material for power electronics due to its high critical electric field, rapid switching, and high-temperature capabilities. This study delves into the dynamic and thermal performance of a novel SiC power MOSFET, utilizing an innovative vertical Gate All Around (GAA) design. Through detailed 2D TCAD simulations in cylindrical coordinates, the device’s behavior is analyzed across various pillar radii and temperatures. Results indicate that while reducing the pillar radius does not improve the on-resistance (RON), a 500 nm radius is required to achieve RON < 10 mΩ∙cm2. Additionally, larger pillar radii significantly increase capacitance. The device exhibits strong switching performance comparable to commercial counterparts and benefits from the absence of a termination region. However, its short-circuit ruggedness is compromised, particularly in structures with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm radius, the temperature peak occurs on the Drain side, a deviation from typical behavior. Despite its advantages, the design's low short-circuit capability remains a limitation.

A detailed numerical study of the dynamic behavior of 3D 3.3 kV SiC MOSFETs constructed with a conventional planar and Quasi-Planar Trench (QPT) design is conducted in this research. The motivation behind this research is to understand the concept and working of QPT, examining its merits and demerits. Static simulations were performed to obtain transfer and output characteristics, threshold voltage, and ON-Resistance (RON) - offering insights into the conduction behavior of the device. Further, the switching losses are examined and comparisons between the two structures is investigated with the help of advanced 3D TCAD simulations at both ambient and high temperature. Accordingly, the present study focuses on dynamic switching simulations, including Turn-ON, Turn-OFF, and Reverse Recovery conditions. The results of this research indicate that while the trench design can benefit from faster conduction and reduced RON, its reverse recovery and the tailing current during Turn-OFF significantly increases energy dissipation. The acquired insights throw light on the QPT architecture’s capability to push the limits of high-voltage SiC based power devices.

This study investigates the static and Short-Circuit performance of a 3.3 kV semi-Superjunction (SJ) MOSFET using TCAD simulations, benchmarked against a fabricated conventional planar MOSFET. The proposed design is based on the cost-effective trench etching and side-wall implantation fabrication method. The analysis demonstrates a wide implantation window, defined by SC withstand time (SCWT) and maximum blocking voltage (BV) performance. Compared to the fabricated MOSFET, the proposed semi-SJ design achieves a 22% improvement in on-state resistance (Ron) and an 11% increase in maximum BV.

High Temperature Reverse Bias (HTRB) testing is a critical reliability assessment for power semiconductor devices, evaluating long-term stability under high reverse bias conditions. While leakage current is the primary parameter monitored, mechanical stress from thermal expansion can also impact device reliability. This study introduces a novel approach for on-line strain monitoring of the package during HTRB using Fiber Bragg Grating (FBG) sensors. A TO-247 high-voltage Si diode was equipped with two FBG sensors to simultaneously monitor temperature variations and mechanical deformations. Experimental results demonstrate that strain variations correlate with leakage current fluctuations, suggesting that mechanical deformation influences leakage current evolution. This technique provides valuable insights into degradation mechanisms in power devices, enhancing the reliability assessment of HTRB testing. The proposed method enables real-time monitoring of thermal and mechanical stress, offering a new perspective for evaluating failure mechanisms in power semiconductors.

This study describes the design and optimization of a 3.3 kV silicon carbide (SiC) semi-super junction(semi-SJ) Schottky barrier diode (SBD). The proposed structure features a 7 mu m deep trench filled with silicon dioxide (SiO2). Aluminum (Al+) sidewall implants are carried out, which help to form a charge balance region. The ON-state improvement of the proposed semi-SJ structure is 16.2%, compared to a planar diode. This results in a specific ON-state resistance (R-ON,R-SP) of 6.2 mcm(2), which surpasses the unipolar limit. The article also addresses the issue of poor blocking voltage performance associated with conventional termination techniques. To mitigate this problem, novel termination designs, which incorporate double-zone junction termination extension (DJTE) and optimally placed rings, are proposed and verified through technology computer-aided design (TCAD) simulations. The most promising structure allows, for the first time, for both a wide implantation window and a high breakdown voltage, reaching 98.3% (4365 V) of the ideal active cell breakdown.