This paper investigates the avalanche robustness of high-voltage silicon PiN diodes under unclamped inductive switching (UIS) conditions. Devices were experimentally tested across a wide range of load inductances. A pronounced reduction in robustness - both in time-to-failure and in maximum avalanche current - was observed at low inductance values, deviating from previously reported monotonic trends. These results indicate the presence of an additional electrically driven failure mechanism, distinct from the classical energy-driven avalanche failure. Based on the experimental evidence and failure analysis, two complementary failure mechanisms are proposed to explain the observed behavior: (i) an energy-driven mechanism, supported by TCAD simulations, and (ii) an electrically driven mechanism, for which a working hypothesis is formulated based on prior literature.

In this study, the surge current capability of a 60 A-1200 V 4H-SiC diode fabricated by paralleling two 30 A dies is experimentally evaluated. Three bond wire configurations are investigated using a non-repetitive surge current test at 25 degrees C and 110 degrees C. The results reveal that the stitch configuration, which employs 3 x 20 mil bonding wires, significantly outperforms the alternative 4 x 15 mil and 4 x 12 mil counterparts in terms of maximum surge current robustness. An extensive analysis is also conducted to identify key differences in the failure mechanisms among the three configurations during surge current stress.

SiC MOSFETs still suffer from some open issues, such as the high density of defects existing at the SiC/SiO 2 interface. Traps distribution at such interface is complex and it affects the overall performance of the device. Traps influence both current-voltage (I-V) and capacitance-voltage (C-V) characteristics of a SiC MOSFET. In this work, we study the relation of Gate capacitance with biased Drain and transconductance with the aim of investigating the channel properties. The analysis is performed using both experimental setup and numerical framework. Experimental and numerical results both exhibit a sharp capacitance peak in the inversion region at a voltage where transconductance reaches its maximum.

Leakage current is a key reliability indicator for power semiconductor devices, as its evolution under stress directly reflects degradation mechanisms. High Temperature Reverse Bias (HTRB) testing provides a standardized procedure to monitor this parameter over prolonged operation under elevated temperature and high reverse-bias conditions. Beyond electrical degradation, the test can also reveal reliability issues associated with thermally induced mechanical stress, which may alter the epoxy mold compound package. To investigate this phenomenon, this study presents a novel approach for real-time strain monitoring of the package during HTRB. As sensor, fiber-optic technology was considered. Particularly, Fiber Bragg Grating (FBG) strain sensors were glued on a TO-247 high-voltage Silicon diode. To validate the proposed methodology, two distinct bonding configurations of the FBG sensor were evaluated. In configuration (a), the FBG is bonded along its full length using an epoxy layer, whereas in configuration (b) the fiber is attached to the package only at two discrete points. In both cases, the measured strain variations exhibit a clear correlation with the evolution of the leakage current, confirming that mechanical deformation influences the leakage current behavior under stress conditions. These results demonstrate the feasibility of using FBG-based strain monitoring to track package deformation and its coupled electro-thermal response during HTRB qualification.

In this paper, a new trench shielding concept against high electric fields is presented by means of an experimental demonstration backed up with 3D TCAD simulations. The novel concept has been applied on an advanced 3D Quasi-Planar Trench (QPT) SiC MOSFET rated at 1200 V and 50 A. The protection approach consists of two key design pillars by employing: 1) shallow trench depths embedded in deeper P-Well Channel regions which are accordingly 2) shallower than deeper highly doped P-Body regions under the source contact. This design provides a double protection scheme for enhancing the device blocking performance and shielding the gate oxide at the critical regions along the trench MOS gate structure. Three different QPT design structures were examined with varying protection levels, with each design having a consistent trench depth but varying trench dimensions across the JFET region (QPT1 with no embedded Trench in P-Well), P-body (QPT2 with partially embedded trench in P-Well), and into the N+ source region (QPT3 with fully embedded trench in P-Well). The blocking characteristics, including the off-state leakage behaviour, were analyzed for the proposed device structures. The optimized QPT structure performs showcases BV performance close to the best-in-class reference planar structure with a deviation of only ~ 0.3 %. The experimental results were further validated through advanced 3D TCAD simulations, which examined electrostatic behavior, and studied electric field distributions along different cross-sections of the trench.

This work presents a custom High Temperature Reverse Bias (HTRB) platform designed for accelerated screening of encapsulation mold compounds in power devices. The system enables parallel testing with real-time leakage current monitoring and in-situ reverse I–V acquisition under controlled temperature and humidity, allowing early detection of thermal runaway. The platform was validated on commercial 1.2 kV diodes encapsulated with two different compounds. Results show that low sodium ion concentration is more critical for long-term reliability than a high glass transition temperature. The setup can serve as a preliminary screening tool to guide compound selection before conducting time-intensive 1000-h qualification HTRB.

Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are essential in modern electronics, enabling efficient power conversion and control in a wide range of applications. Wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) have been shown to boost device performance, by providing higher efficiency and faster switching for high-power, high-frequency applications. Although optimised for standard operation, their performance under short circuit (SC) events remains critical mostly because of the higher current density. Notably, SiC MOSFETs can only withstand SC conditions for a few microseconds, necessitating larger layouts or faster control electronics to prevent the catastrophic failure of the device. This paper introduces a novel power device, the Ferro-Power MOSFET, that integrates a ferroelectric material into the gate stack of a power SiC MOSFET. This innovative approach leverages the temperature-dependent dielectric constant of ferroelectrics to effectively reduce the temperature rise during short-circuit events without altering the basic layout of the device neither the control electronics. TCAD simulations and design optimisation of a 1.2 kV SiC MOSFET reveal substantial enhancements, achieving temperature and current reductions of up to 31% and 42%, respectively, without compromising current conduction during normal operation. It stands to reason that this concept is general and can be broadly applied to any power MOSFET. Moreover, it is bolstered by recent achievements in ferroelectricity in CMOS-compatible hafnium oxide (HfO2), thus prospecting concrete experimental developments in power semiconductors.

In this paper, we introduce a compact model tailored for silicon carbide Merged PiN Schottky (MPS) diodes in the form of a SPICE-compatible subcircuit. The model is designed to (i) describe the undesired snapback mechanism, which is likely to occur in unoptimized diodes with narrow width of the PiN portion and/or excessively thick drift layer, (ii) capture the dependence of geometry-related parameters upon the width of the cell and the individual widths of the PiN and Schottky portions, (iii) account for the impact of temperature on the related parameters; in addition, the thermal equivalent of the Ohm's law is exploited to allow for static and dynamic electrothermal simulations within SPICE-like tools. The proposed subcircuit is adopted to analyze imbalances occurring in paralleled snapback-affected MPS diodes subjected to current surge events.

This paper presents a novel High-Temperature Reverse Bias testing platform designed for real-time, automated monitoring of leakage current in multiple high-voltage devices under uniform stress conditions. The setup enables accelerated stress testing at elevated temperatures while ensuring thermal safety and minimizing manual intervention. A case study is conducted on two identical 1200 V silicon diodes encapsulated with different epoxy mold compounds (EMCs) to evaluate the system's screening capabilities. Experimental results show significant post-stress degradation in devices with higher sodium content including, increased leakage and reduced breakdown voltage. Additional degradation effects, such increased leakage at low voltage, are also observed. TCAD simulations reveal that localized donor-like traps at the $\text{Si} / \text{SiO}_{2}$ interface can explain the experimental findings, suggesting a failure mechanism linked to ionic contamination in the termination region. The study demonstrates the platform's effectiveness for comparative reliability screening and failure mode analysis.

Silicon carbide (SiC) power MOSFETs are widely used in high-voltage applications for their superior electrical and thermal properties. The SiC Gate-All-Around (SGAA) structure enhances performance by eliminating termination regions and enabling high breakdown voltage and current density. However, localized heating during short-circuit events limits its robustness. This work proposes the integration of a ferroelectric layer (e.g., HfO2) into the SGAA gate stack—forming the FERRO POWER SGAA—to exploit temperaturedependent dielectric behavior and improve thermal management. TCAD simulations confirm enhanced robustness and reduced current overshoot during transient conditions.

Silicon Carbide (SiC) is a leading material for power electronics due to its high critical electric field, rapid switching, and high-temperature capabilities. This study delves into the dynamic and thermal performance of a novel SiC power MOSFET, utilizing an innovative vertical Gate All Around (GAA) design. Through detailed 2D TCAD simulations in cylindrical coordinates, the device’s behavior is analyzed across various pillar radii and temperatures. Results indicate that while reducing the pillar radius does not improve the on-resistance (RON), a 500 nm radius is required to achieve RON < 10 mΩ∙cm2. Additionally, larger pillar radii significantly increase capacitance. The device exhibits strong switching performance comparable to commercial counterparts and benefits from the absence of a termination region. However, its short-circuit ruggedness is compromised, particularly in structures with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm radius, the temperature peak occurs on the Drain side, a deviation from typical behavior. Despite its advantages, the design's low short-circuit capability remains a limitation.

A detailed numerical study of the dynamic behavior of 3D 3.3 kV SiC MOSFETs constructed with a conventional planar and Quasi-Planar Trench (QPT) design is conducted in this research. The motivation behind this research is to understand the concept and working of QPT, examining its merits and demerits. Static simulations were performed to obtain transfer and output characteristics, threshold voltage, and ON-Resistance (RON) - offering insights into the conduction behavior of the device. Further, the switching losses are examined and comparisons between the two structures is investigated with the help of advanced 3D TCAD simulations at both ambient and high temperature. Accordingly, the present study focuses on dynamic switching simulations, including Turn-ON, Turn-OFF, and Reverse Recovery conditions. The results of this research indicate that while the trench design can benefit from faster conduction and reduced RON, its reverse recovery and the tailing current during Turn-OFF significantly increases energy dissipation. The acquired insights throw light on the QPT architecture’s capability to push the limits of high-voltage SiC based power devices.

This work presents the development of a low-power embedded system for real-time detection of obstructive sleep apnea (OSA) events using tracheal body sound analysis. The proposed system performs artificial intelligence at the edge, executing all signal acquisition, preprocessing, and inference directly on-device, without reliance on internet to cloud connectivity. The hardware platform integrates an STM32F7 ARM Cortex-M7 microcontroller alongside an electret microphone and an inertial measurement unit (IMU), enabling flexible sensing of tracheal vibrations through both acoustic and inertial modalities. Audio data from the PSG-Audio dataset were preprocessed into Mel spectrograms and used to train a lightweight Convolutional Neural Network (CNN) optimized for embedded deployment. The final quantized model achieved a preliminary accuracy of 87.06 %. Experimental measurements demonstrated an inference time of 219.4 ms and an average current consumption, during the inference time, of 109.86 mA at 216 MHz. These results underscore the feasibility of integrating audio-based OSA detection into wearable electronic sensors, supporting continuous, real-time physiological monitoring at the edge.

High Temperature Reverse Bias (HTRB) testing is a critical reliability assessment for power semiconductor devices, evaluating long-term stability under high reverse bias conditions. While leakage current is the primary parameter monitored, mechanical stress from thermal expansion can also impact device reliability. This study introduces a novel approach for on-line strain monitoring of the package during HTRB using Fiber Bragg Grating (FBG) sensors. A TO-247 high-voltage Si diode was equipped with two FBG sensors to simultaneously monitor temperature variations and mechanical deformations. Experimental results demonstrate that strain variations correlate with leakage current fluctuations, suggesting that mechanical deformation influences leakage current evolution. This technique provides valuable insights into degradation mechanisms in power devices, enhancing the reliability assessment of HTRB testing. The proposed method enables real-time monitoring of thermal and mechanical stress, offering a new perspective for evaluating failure mechanisms in power semiconductors.

Single-Flux-Quantum (SFQ) logic is a digital electronic technology known for its very low-power consumption (nW-µW) and high operating frequency (up to 100 GHz). Like any other device, SFQ-based logic circuits suffer from manufacturing process issues, specifically concerning variations in the determined values of individual components such as the critical current of a Josephson junction and inductances. This leads to the need for a deep understanding of the circuit performances, its tolerance range and, furthermore, an optimization tool to improve it achieving a certain margin for each component. In this regard, the present article delves into the techniques and the development of a new design parameter optimization algorithm, whose main goal is to increase the critical margin of the circuit. By using such a simple and efficient technique, failures due to the fabrication are avoided and performance enhancement is achieved.

Infrared thermography has shown great promise as a diagnostic method for health care, providing useful information on a person's physiological, and pathological state. Recently, the use of artificial intelligence combined with infrared technology has boosted the adoption of thermal imaging in various applications and has been proposed to recognize human emotion by measuring facial skin temperature. However, its application has been limited to laboratory settings due to demanding computational and hardware resources. In this scenario, this work presents the design and development of a portable system based on a low power microcontroller implementing an optimized Edge-AI solution for binary emotional state classification using minimal hardware resources. The recognition of happiness and sadness emotional states induced by audiovisual stimuli serves as a case-study for feasibility assessment. Thermal images, produced by an uncooled and low-cost thermal sensor, along with electrocardiogram, are acquired and processed with an Arm® Cortex®-M4 microcontroller. A simple, yet effective neural network has been developed, optimized, and deployed to run the emotion detection algorithm in real time. The complete system has been experimentally verified and results in terms of accuracy and hardware constraints are discussed. Specifically, by employing a dataset consisting of 60 infrared videos, an accuracy of 80

In this paper a novel timing system for alpine ski races is presented. The proposed system is composed by a starting gate, a finish line detector, a trainer handheld device and an athlete device that can be repeated for any number of athletes. Each device is based on a ESP32 microcontroller and all athletes’ devices communicate with the starting gate, finish line and trainer handheld using the ESP-NOW protocol. The athlete device is completed by an accelerometer used to disambiguate a running athlete from the others on the starting or finish line.

In this paper, a simple compact model for the static behavior of SiC MPS diodes is developed in the form of a SPICE-compatible subcircuit. The model is suited to describe the undesired snapback mechanism likely to occur in unoptimized high-voltage MPS structures with narrow width of the PiN portion and/or very thick drift layer; in particular, the model accounts for the snapback mechanism both as the cell extension varies and as individual portions of Schottky and PiN vary. Sentaurus TCAD simulations of a 10-kV MPS diode are used as a reference for the calibration of the model parameters and accuracy verification.

This paper provides an experimental investigation through infrared thermography of the steady-state temperature imbalance arising in parallel SiC MOSFETs. A switched-mode boost power converter based on two arrays of 4 parallel 1.2 kV MOSFETs is selected as a case-study. The analysis aims at proving that a proper device arrangement can minimize the thermal imbalance in the absence of circuit layout optimization.

This article describes the design, characterization, development, and preindustrialization of a novel interrogation system for fiber Bragg grating (FBG) sensors capable of taking advantage of the Internet-of-Things (IoT) technology. Due to its complexity and cost, classical interrogation systems limit the design and use of a sensor network based on fiber-optic technology that is often replaced with less performant electronic sensor systems. The proposed system has the potential to overcome the limits of today's commercial interrogators, converting the classic FBG interrogator into an IoT node, where each circuit is represented by a sensory node that continuously exchanges and publishes data on the cloud. Moreover, the proposed concept may be applied in harsh environments, still taking advantage of the fiber-optic technology. The interrogator is composed of a passive optical device section and a four-layer electronic board section (one board for each connected FBG in the external array), which conditions the optical signal to a compliant voltage at the downstream analog-to-digital converter (ADC). In the subsequent digital processing section, created inside an ARM-based board, the conversions are then carried out through dedicated algorithms to match the voltage variation to the Bragg wavelength shift and the subsequent conversion into the relative physical quantity (temperature, deformation, or humidity) via a subsequent conversion algorithm. Finally, physical values, in real-time, are published on a remotely accessible server. The proposed system was tested and validated by comparing data produced by commercial interrogations. The tests were performed using an array composed of six independent FBG sensors. It was tested through stability and on-field measurements, detecting one temperature-compensated strain point and four temperature-monitoring points.