The increasing demand for secure hardware systems has intensified the need to evaluate vulnerabilities against noninvasive attacks such as side-channel attacks (SCA), which can extract secret information without altering device functionality. Elliptic Curve Cryptography (ECC)-based algorithms are widely adopted due to their strong security and efficiency; however, ensuring their resilience at the hardware level remains a critical challenge. In this paper, we present a customized ECC-based ECDH hardware design incorporating a Karatsuba-based multiplication architecture optimized for efficient implementation. To assess security, a pre-silicon side-channel leakage analysis is performed at the RTL level using power trace evaluation and a t-score-based statistical framework. The results demonstrate that leakage is input-dependent and can be localized to specific stages of computation, particularly the initial stage of the design. Unlike conventional post-silicon approaches, the proposed methodology enables early-stage detection and localization of leakage-prone regions at the RTL level, providing actionable insight for targeted countermeasure integration and improved hardware security.

Electromagnetic Fault Injection (EMFI) is a critical threat to the security and reliability of integrated circuits (ICs), capable of causing data corruption, system failures, and information leakage. To address these challenges, we propose a novel machine learning-driven framework for efficient EMFI analysis in the pre-silicon design stage. Our approach integrates electromagnetic simulation, machine learning guided modeling, and layout level voltage-current analysis to accurately predict induced currents and evaluate their impact on IC performance and security. A core innovation of this work is the machine learningguided identification of “cutout” regions-areas most impacted by EM fault injection-significantly reducing simulation runtime while maintaining high accuracy. The framework trains a model on a diverse dataset of metal layer configurations and coil distances and thus, allows precise targeting of critical areas for simulation. Finally, by analyzing dynamic current distribution across critical metal layers, the method effectively assesses design robustness against EMFI-induced timing violations and faults. Experimental results demonstrate that this framework achieves a substantial reduction in simulation run-time compared to traditional full-geometry approaches. Furthermore, the simulation results are validated by experimental data, confirming the framework's accuracy and reliability. Thus, this framework provides a practical, fast, and scalable solution to enhance IC security and reliability against EMFI.

This study applies machine learning to side-channel attacks and proposes an iterative transfer learning method for deep learning models. This study leverages the similarity in training patterns across bytes by first training on a single byte and then using the resulting model as a pretrained foundation for the remaining bytes. This approach enables effective model training with smaller amounts of data while reducing the measurement-to-disclosure (MTD, i.e., the minimum number of traces needed for successful key recovery) in the attack phase. With sufficient data, iterative transfer learning reduces MTD from 55 to 54 using MLP and from 125 to 83 using CNN. Even under limited data conditions, it successfully breaks AES-128 while reducing training samples from 13,600 to 2,000, achieving an average MTD of 635, whereas traditional methods fail. Experimental results demonstrate that the iterative transfer learning approach addresses the persistent data scarcity challenge in deep learning, significantly expanding the applicability of deep learning methods in side-channel attack scenarios.

This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.

Thermal issues of 3D-ICs have become increasingly severe in recent years. Thus, thermal simulation is needed to ensure thermal safety during the design stage. However, performing thermal simulation iteratively requires a significant amount of time. As a result, a fast and accurate method for thermal prediction is a promising alternative to improve the turnaround time. In this paper, we propose a fast thermal prediction method using machine learning models. In the training phase, we employ two models: one for the initial three time steps and another for the subsequent time steps. To enhance prediction accuracy, we introduce two types of features: spaced-windowed features and time-decayed features. These features help us to capture spatial and temporal information effectively. In our experiment, the mean absolute error for the predicted temperature is 1.12 degrees C, and the maximum error is 7.27 degrees C. In the prediction phase, we achieve a 116X speed-up compared to a commercial tool. With our proposed method, users can predict transient thermal profiles quickly and accurately to ensure thermal safety.

Thermal management is critical for 3DIC design because stacking dies vertically increases power density and peak temperature and creates thermal hotspots, which can significantly impair transistor reliability, degrade performance, and accelerate device aging. Conventional static and transient thermal analysis approaches use finite element method (FEM) and computational fluid dynamics (CFD) to provide detailed and accurate thermal profiles of chips. However, they are computationally intensive and impractical for today’s large-scale 3DIC designs. Recently, machine learning (ML) is used to accelerate thermal predictions, but a sufficiently large training dataset is needed to re-train or fine-tune models for chips of different dimensions and/or power distributions. In this paper, we propose a multimodal learning-based framework that can effectively learn from limited training data and accurately predict the thermal behavior of diverse chip configurations. The model is trained only once with data of fixed size, which is much smaller than that required by the current ML methods. Compared to a commercial electrothermal simulator, our approach achieves a 150× speedup of runtime and requires only 0.023% of the memory. On chips of different die sizes, our model’s prediction error is within 2.63% of the thermal prediction of a commercial simulator, and less than 3.72% for real-life power patterns.

A large on-chip peak temperature and thermal gradient, caused by localized hotspots and cross-die thermal coupling, can severely impact transistor performance, stress, aging, electromigration (EM), voltage drops, and timing. Generating static and transient chip thermal profiles with traditional FEM/CFD methods have prohibitively expensive computational requirements, especially for three-dimensional integrated circuits (3DIC). Even though data driven based deep learning approaches can significantly improve the efficiency of obtaining accurate thermal profiles, large amounts of high-quality and diverse training data are required. Therefore, there is an urgent need for improving the data/training efficiency and generalizability of deep learning-based models for thermal applications. This investigation leverages the "linear superposition principle" for linear systems and divides a complex power pattern into "per-tile activation" scenarios. The predictions from machine learning (ML) model trained on per-tile activation data, which consists of power and thermal response pairs, are then linearly combined to generate the total thermal response for a given arbitrary power pattern. This novel approach can substantially reduce the infinite design space of the power patterns to a small finite design space, and it has been validated that it can significantly improve the generalizability and training efficiency of deep learning models. The proposed approach can be applied to static and transient chip thermal simulation for 3DIC.

3D Heterogeneous Integration (3DHI) of copackaged optics (CPO) emerges as a promising low-power, lowlatency, and high-bandwidth IO solution for the ever-growing datacenter, AI and IoT applications. However, the design and co-optimization of heterogeneous integration of electrical and photonics system is very challenging by multiscale modeling and multiphysics integrity concerns. In this work, a novel thermal simulation solution is proposed to tackle the model accuracy, mesh fidelity and multi-scale challenges. A typical CPO design in 3DHI stacking system has demonstrated a comprehensive workflow to handle heater ring and waveguide structures and predict the vertical thermal coupling effects and thermal hotspots of the entire SiPh system.

Optical side-channel analysis poses a significant threat to the security of integrated circuits (ICs) by enabling the disclosure of secret data, such as encryption keys. In this paper, for the first time, we present a multiphysics simulation framework of optical side-channel analysis from the layout database of a fabricated testchip. By leveraging accurate device models and electro-photonic physics, our framework models the photon emission behavior in ICs and enables the statistical correlation of emitted photon patterns with secret keys. Our framework enhances understanding of layout-level optical side-channel leakage and its implications, enabling IC designers to assess the risks associated with optical side-channel attacks and develop efficient countermeasures at the pre-silicon stage.

The emerging 3D-IC systems, enabled by advanced packaging techniques, promise high integration density and manufacturing yield to keep Moore's Law thriving. However, due to the complexity of heterogeneous integration of various chiplets into the chip-package-system, applications built upon 3D-IC are challenged by power integrity, signal integrity, thermal integrity, and structural integrity issues. Design and analysis of 3D-IC requires multiphysics simulation to meet the overall performance, power, thermal, and reliability targets. In this paper, we demonstrate a comprehensive EDA platform that enables 3D-IC multiphysics simulation from early architecture planning to design signoff stages. Benefiting from the 3Dblox flow, assembly of 3D-IC systems with millions of microbumps or hybrid bonding can be achieved to facilitate a holistic chip-package-system multiphysics simulation. Finally, this platform enables a novel system co-optimization methodology through a machine-learning-assisted approach to address multiphysics design and optimization challenges.

Near-field electromagnetic fault injection (EMFI) is one of the most commonly used attack methods to intentionally cause errors in digital circuits due to its inherent advantages. A full-wave simulator was used to analyze the voltage fluctuations on the on-chip power mesh excited by EMFI. We have described the relationship in which the shape of the voltage fluctuations on the power mesh inside ICs is derived from the differentiation of the current flowing through the injection coil by using Maxwell’s equations and full-wave simulations. In addition, the results with different injection positions and ideal voltage source points have showed that the areas of high sensitivity vary on the power supply mesh.

Excessive dynamic IR-drop in VLSI testing causes timing violations, which leads to test failure. The dynamic IR-drop becomes a more serious problem in at-speed two-vector tests than that in stuck-at tests due to the at-speed clock. However, we need Machine Learning methods to speed up the analysis because of the long runtime of dynamic IR-drop analysis. In this paper, we propose two new methods to predict dynamic IR-drop of at-speed two-vector tests. One uses two models for the first capture cycle and the second capture cycle, respectively. The other one combines features of two capture cycles. Also, we propose spaced-window features and time-sliced features to improve prediction accuracy. Our mean absolute error for the worst dynamic IR-drop prediction is S.230m V, which is less than 0.6 % of the supply voltage. Our experiment results show at least a 12.6X speed-up ratio compared to a commercial tool. With our technique, we can identify two-vector tests which have excessive IR-drop in a short time to prevent yield loss.

Generally, the tolerance of cryptographic modules implemented in application-specific ICs (ASICs) to side-channel (SC) attacks is evaluated after the silicon manufacturing stage. This post-silicon assessment presents two significant challenges. First, manufacturing ASIC chips is both costly and time-consuming. Second, while post-silicon evaluation can determine the effectiveness of countermeasures, it cannot identify the source of unexpected leakage. Therefore, simulation-based SC leakage assessment is crucial as it allows for SC leakage evaluation before manufacturing and facilitates immediate revisions if the desired SC leakage tolerance is not achieved. In this paper, we propose a hybrid simulation approach, which combines logic-based simulations and transistor-level simulations. We demonstrate that this simulation approach meets two essential features for side-channel leakage assessment, simulating at the transistor-level with high accuracy at the cryptographic core-level and estimating the signal-to-noise ratio (SNR) considering the entire chip, while achieving high speed of collecting 1,000 waveforms in 300 hours, which is 282 times higher efficiency compared to the traditional chip-level transistor simulation.

Integrated circuit (IC) chips equipped with crypto circuits are susceptible to side-channel (SC) attacks that exploit SC information derived from the operation of the crypto circuit to reveal the secret keys. In this paper, we focus on the Si substrate voltage on the backside of the IC chip. The use of flip-chip implementations has led to the emergence of a new threat: direct probing attacks on the Si substrate. In this paper, we present a novel Si-backside voltage simulation method that extends the Chip Power Model (CPM). Furthermore, we analyze the Si-backside voltage and evaluate the SC leakage.

Cryptography hardware is vulnerable to side-channel (SC) attacks on power supply current flow and electromagnetic (EM) emission. This article proposes simulation-based power and EM side-channel leakage analysis (SCLA) techniques on a cryptographic integrated circuit (IC) chip in system level assembly. SCLA measures SC leakage metrics including T-score, SC leakage score, and the number of measurement traces to disclosure, leveraged by a secure system-on-chip design flow toward SC attack resiliency and SC leakage sign off. Power SCLA features the tracking of security sensitive registers within cryptographic logic paths and the automatic assignments of probe points on associated physical power nets. Power supply current traces are efficiently simulated for the large set of input payloads, with direct vector-based and vector-less random switching controls. EM SCLA evaluates magnetic fields created by every piece of metal wiring in metal stacks where power supply current of cryptographic processing flows. The EM emission and EM SCLA from the backside Si surface of an IC chip in flip-chip packaging are experimentally examined with a 0.13 μm test chip. The proposed simulation-based SCLA exhibits the SC leakage metrics of on-chip location and direction dependency as accurately as in the measurements.

Static chip thermal analysis provides detailed and accurate thermal profile on chip. The chip power map, commonly modeled as rectangular regions of distinct heat sources, significantly impacts the chip thermal profile. Since the heat sources result from numerous cells in functional blocks, the design space of chip power map is prohibitively enormous. Numerical simulations can be reliable for solving complex power maps; however, it could be very time-consuming when simulating a large SoC and/or 3DIC designs. Thus, there is an urgent need for speeding up the static chip thermal analysis to tackle various power maps. In this paper, we propose an approach of integrating our developed machine learning thermal solver [1] and decay curve characterization for solving static chip thermal with diverse power maps. The machine learning thermal solver would first solve the power maps on a coarse level (e.g., 200 um). The thermal results are further enhanced using the decay curve algorithm which would fine tune the solution locally provided by the machine learning thermal solver and calculate the local temperature variations at a finer level (e.g., 10 um). The deep learning models are trained on augmented artificial power maps and tested on realistic chip power maps. Experimental results validate the effectiveness of the proposed approach of offering fast and accurate chip thermal profile.

Laser fault injection (LFI) is a formidable physical attack due to its tremendous efficacy, high controllability, and precision. As a result, efforts to simulate laser effects have been undertaken in the literature to study its impact on digital designs. However, most of these efforts either model laser effects on standalone standard cells without considering the impact of layout parameters or propose scanning the entire chip grid-by -grid, which is extremely time-consuming to simulate at the layout level. In this paper, we propose LFI-aware sign-off solution for layouts to analyze the designs for LFI susceptibility and apply countermeasures. We employ security properties driven evaluation to identify critical LFI areas on the layout to reduce scanning time. And then perform dynamic power and rail analysis while replacing the cells under laser illumination with the generated cell-level power library, capturing the impact of laser-induced transient currents on the entire layout. Because the assessment is done at the layout level, the framework can capture the impact of different layout parameters (location of power pads, metal widths, power distribution network, DECAPs, etc.) while analyzing the design's susceptibility against LFI attacks to see which security properties of the design will be violated if laser faults are injected at the identified critical locations. We show the effectiveness of our approach on a fully implemented AES design layout for the proof-of-concent.

Trusted microelectronics are increasingly threatened by fault injection attacks through a variety of physical means. Electromagnetic fault injection (EMFI) is a low-cost but effective approach to induce parasitic currents on a victim chip. To address the gap between logic fault principle and silicon EMFI mechanism, a layout-level simulation methodology to identify physical vulnerabilities of the victim chip is needed. In this paper, a fast numerical inductance solver is proposed to characterize the location-dependent coupling effects between EM field signal and on-chip wires. To validate the simulation accuracy, the result from our solver is calibrated with a 3D EM field solver to achieve great correlation. Leveraging parallel computing techniques, our tile-based simulation on a large design has been demonstrated as an accurate and effective ranking of EMFI vulnerabilities of the victim chip.

Laser-based fault injection (LFI) attacks are powerful physical attacks with high precision and controllability. Therefore, attempts have been in the literature to model and simulate the laser effect in pre-silicon digital designs. However, these efforts can only model the laser effect on small SPICE or TCAD circuits of individual standard cells. This paper proposes security properties and a machine-learning assisted layout signoff framework in verifying the full-chip layout's resiliency against LFI. In the framework, we leveraged the commercial SoC power integrity sign-off tool to inject the Gaussian laser current to any spot in the layout, by considering different layout features such as power distribution network, decoupling capacitor placement, metal geometry, instance switching power, etc. To avoid exhaustive analysis of all layout spots regardless of LFI criticality, we use security properties to drive the assessment and identify critical areas. We then use SPICE simulations and machine learning to develop cell-level laser fault models under different laser-induced transient current intensities. This laser cell library is used during full-chip LFI feasibility analysis for the cells inside laser illumination, enabling precise layout -level design fix for critical cells failing the fault injection threshold. Finally, we show the effectiveness of the proposed framework by analyzing the fully implemented AES design layout.

Accurate side-channel attacks can non-invasively or semi-invasively extract secure information from hardware devices using "side- channel" measurements. The thermal profile of an IC is one class of side channel that can be used to exploit the security weaknesses in a design. Measurement of junction temperature from an on-chip thermal sensor or top metal layer temperature using an infrared thermal image of an IC with the package being removed can disclose secret keys of a cryptographic design through correlation power analysis. In order to identify the design vulnerabilities to thermal side channel attacks, design time simulation tools are highly important. However, simulation of thermal side-channel emission is highly complex and computationally intensive due to the scale of simulation vectors required and the multi-physics simulation models involved. Hence, in this paper, we have proposed a fast and comprehensive Machine Learning (ML) augmented thermal simulation methodology for thermal Side-Channel emission Analysis (SCeA). We have developed an innovative tile-based Delta-T Predictor using a data-driven DNN-based thermal solver. The developed tile based Delta-T Predictor temperature is used to perform the thermal side-channel analysis which models the scenario of thermal attacks with the measurement of junction temperature. This method can be 100-1000x faster depending on the size of the chip compared to traditional FEM-based thermal solvers with the same level of accuracy. Furthermore, this simulation allows for the determination of location- dependent wire temperature on the top metal layer to validate the scenario of thermal attack with top metal layer temperature. We have demonstrated the leakage of the encryption key in an 128-bit AES chip using both proposed tile-based temperature calculations and top metal wire temperature calculations, quantified by simulation MTD (Measurements-to-Disclosure).