Modern low-power wireless communication systems often operate under strict energy and area constraints, especially in edge and embedded platforms. This paper proposes novel optimization techniques for Multi-Level-Cell STT-MRAM (MLC STT-MRAM), replacing SRAM for an area- and energy-efficient Viterbi decoder in wireless communication. Three key techniques are introduced to mitigate the performance and energy consumption overhead of MLC STT-MRAM while preserving its high area efficiency. First, the energy barrier optimization technique is proposed, leveraging the fact that the survivor memory of the Viterbi decoder does not need to hold its data for a long period. This optimization significantly reduces the write energy. Second, the sequential-access-aware cell-split-mapping (SAA CSM) method exploits the sequential memory write and read access patterns of the Viterbi decoder, enabling a one-step write. Third, the column selective read technique utilizes column multiplexers within the memory peripheral circuits, eliminating unnecessary read operations and their associated circuits, thereby reducing power consumption and area. The proposed Viterbi decoder, compatible with IEEE 802.11n/ac, is implemented in a 28-nm CMOS technology, achieving 17.24% area and 55.15% energy reduction compared with a conventional MLC STT-MRAM-based design. Even compared with the conventional 6T SRAM-based design, proposed design achieves 51.94% and 9.09% reduction in area and energy consumption, respectively, without performance degradation.
Deoxyribonucleic Acid (DNA) storage is promising to be an ultimate data storage solution with ultra-high storage density and long durability. A DNA storage system encodes and stores digital data with synthetic DNA sequences, and decodes DNA sequences back to digital data via DNA sequencing. Using primers and polymerase chain reaction (PCR) based random access has also been introduced to DNA storage for efficient data retrieval. However, a DNA storage system equipped with PCR-based random access suffers from primer-payload collisions. Primers with this type of collisions cannot be reliably used and must be discarded. Since the numer of usable primers determines the DNA tube capacity, it is critical to reduce the impact of primer-payload collisions and increase the tube capacity. In this paper, we propose to use variable length payloads to recover primers from collisions and enhance DNA storage capacity. With the proposed heuristic algorithms and four payload lengths, the scheme can recover thousands of collided primers with three state-of-the-art encoding schemes. For an existing collision resistant encoding scheme, Rotation code, it can further improve 18.27% of tube capacity, from 217.59 GB to 257.35 GB. For the other two encoding schemes, the improvements of tube capacity are 4.3X and 18,3X. respectively.
Hyperdimensional Computing (HDC), a brain-inspired Machine Learning (ML) technique, excels in edge computing due to its low resource requirement and is now advancing to handle even data-center workloads. By harnessing the advantages of photonics, high-speed and energy-efficient HDC training and inference can be achieved, fostering rapid HDC development. This article introduces PhotoHDC, the first electro-photonic accelerator designed for HDC training and inference, supporting traditional, record-based, and graph encoding. Our microarchitecture employs Mach-Zehnder Modulators and photodetectors to enable high-speed modulation with efficient dataflows optimized for HDC operations. We demonstrate that PhotoHDC can achieve one to four orders of magnitude lower Energy-Delay Product (EDP) than leading electro-photonic Deep Neural Network (DNN) accelerators when running HDC training and inference on popular datasets. We also show that photonics can address the limitations of compute-in-memory-based HDC accelerators, achieving three orders of magnitude lower EDP on average for both training and inference.
In the field of computer science, Convolutional Neural Network (CNN) algorithms are a crucial tool that contributes to the advancement of Computer Vision. CNNs are composed of an enormous number of multiplication and addition operations performed on the input data to calculate the probability and predict the output. In multiplication, if any of the operands is zero-valued, then it is irrelevant in that particular output, and hence, these computations can be omitted to avoid unnecessary computation. In this study, we propose an architecture that performs the computations through parallel Processing Elements(PEs) and is also capable of skipping the ineffectual zero-valued computation to improve PE utilisation. Our proposed work, SpALEn, adopts the channel-first dataflow and is designed to perform the inference function with zero-skipping for enhanced performance. Moreover, due to the skipped computation, load imbalance occurs as the computation workload varies among the PEs. A dynamic logic is designed to mitigate this and ensure the hardware resources are utilised thoroughly. SpALEn achieves a speedup of 12 \(\times\) in comparison to a dense architecture.
The SystemC language, with its higher level of abstraction, plays a critical role in facilitating hardware/software co-design and architecture exploration. However, as most hardware models are predominantly written in Verilog and translating between SystemC and Verilog remains a challenge, an efficient and reliable tool for translating between these two languages is essential to streamline system development. This paper proposes SCAV, a bidirectional translator between SystemC and Verilog, which breaks these limitations. SCAV provides a fully automated solution for translating both SystemC to Verilog and Verilog to SystemC, leveraging a translation framework with front-end/back-end separation. Additionally, SCAV incorporates an Abstract Syntax Tree (AST) filter, optimizing the translation process by filtering out invalid content. The experimental results demonstrate that SCAV achieves a 100% adaptation rate for Verilog and a 98% adaptation rate for SystemC, with 100% accuracy in both directions. Furthermore, SCAV outperforms existing tools, delivering a minimum speedup of 18% across various test cases.
Computing-in-memory (CIM), as a novel computing architecture for the future, effectively overcomes the bottlenecks in the von Neumann architecture. The CIM architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. However, embedding logic into the memory array increases the test complexity. In this study, we offer a comprehensive examination of the challenges associated with CIM and introduce a novel March-like test algorithm, named March CC, tailored for CIM chips. Computational elements are added to the read/write operation sequences, combining the tests in memory mode and computing mode into one step, which significantly improves the test efficiency. In comparison to the traditional March C− test algorithm, the proposed March CC test algorithm, with a complexity of only 10 N , enhances the fault coverage from 66.7% to 79.8% for six common single-cell fault (SCF) models and nine common double-cell fault (DCF) models. Furthermore, the March CC algorithm demonstrates good compatibility and is applicable to various memory configurations, such as SRAM, RRAM, and MRAM CIM architectures.
The Robotic Operating System (ROS) provides resources that facilitate the development of robots. However, these resources do not provide robots with some features required in complex scenarios, such as goal-oriented behaviour, autonomy, deliberative capabilities, social abilities and proactivity combined with reactivity. On the other hand, these features are inherent to Belief-Desire-Intention (BDI) agents, whose behaviour results from reasoning over explicit representations of their beliefs (information about the environment), desires (goals to be achieved) and intentions (commitments to those goals). This work addresses the integration between ROS and BDI agents. This integration is addressed both at a conceptual level, where ROS and BDI concepts are aligned, and in a more practical level, where programming tools are presented to program the behaviour of ROS-based robots as BDI agents. The proposal is evaluated through application examples. The results of this work include an integration model and tools to develop these robots.
Edge devices (ED) play a crucial role in enabling intelligent decision-making capabilities for Smart Cyber-Physical Systems (CPS). Nevertheless, it is a challenging objective, given the resource constraint of edge devices. Pre-trained Machine learning models fail to perform well against real-world data, provided via EDs. Conventional Embodied AI strategies outsource the training load to adapt to real-world data. However, the dependence on outsourcing attracts issues related to latency, privacy, scalability, and so on that are detrimental to a CPS. As a solution, this c proposes ChaoticImmuneNet, a lightweight Embodied AI method that allows onboard learning on resource-constrained EDs, with limited and noisy data. The article introduces a novel strategy, merging techniques from Artificial Immune Systems and Chaos Theory with a Siamese Neural Network for realizing onboard learning. ChaoticImmuneNet differs from Chaotic Neural Networks as the former does not require specialized models and hardware to leverage chaotic dynamics. Experimental studies carried out using three diverse image datasets demonstrate the efficacy of the proposed method when compared with existing onboard learning techniques, in terms of accuracy, time and storage requirements. A real-world deployment of the ChaoticImmuneNet on a real mobile robot, operating within a warehouse prototype testify to its pragmatic utility.
Considering side-channel analysis (SCA) security for cryptographic devices, the mitigation of electromagnetic (EM) leakage and EM interference (EMI) between modules poses significant challenges. This article presents a comprehensive review and deep analysis of the utilization of EMI shielding materials, devised for reliability purposes and standards such as EMI/EMC, as a countermeasure to enhance EM-SCA security. We survey the current landscape of EMI shields materials, including conductive polymers, metal-foams, carbon-based materials, and meta-materials, evaluating their effectiveness in attenuating emissions and preventing information leakage, a task done with security-centric metrics for such materials for the first time. Through a systematic examination of existing literature, experimental studies and a construction of fully simulatable EM environment in ANSYS-solver, we identify key factors influencing the performance of EMI shield materials, such as shielding-effectiveness (SE), bandwidth, thickness, and material properties, on security characteristics. We devise a connection between SE and cryptographic-SNR, and we demonstrate from real hardware measurements how and in what conditions can such materials provide very high security levels. By synthesizing insights from multidisciplinary research domains, this article aims to provide valuable two-way benefit and guidance for researchers, engineers, and practitioners in the design and deployment of robust side-channel security measures leveraging EMI shields, already in utilization devised by reliability standards.
An attacker can modify the actuator inputs, sensor observations, and state of the physical system in a cyberphysical system (CPS), causing errors in the system's proper functioning. It is crucial to investigate a CPS in the presence of all possible attack types to make it resilient. For this, all possible attack sequences must be known. This article focuses on designing false data injection (FDI) attacks on the physical system, actuator input, and sensor measurement in a CPS, individually and in their combined locations. Each attack sequence follows a Gaussian distribution. We study a discrete linear time-invariant (LTI) CPS with a single sensor and actuator. The system also includes a Kalman filter and a Chi-square (x2) detector. With a x2 detector and possible known system parameters, we have proposed seven types of FDI attacks at vulnerable locations based on Kullback-Leibler (KL) divergence. The attacker can remain undetected by carefully planning the attack sequences. The attack increases the state estimation error (SER), and degrades the system's proper operation. The effect of attacks on the detection result and the difference between SER with and without attack is simulated through two examples from the LTI system.
Blockchain technology is a nascent technology that possesses attributes such as immutability, security, transparency, openness, and decentralization. It is widely used in industry and business applications. Though it has the best features, it still suffers from some main characteristics, such as scalability and privacy. Scalability is measured through throughput (transactions per second), space, cost, and latency. Bitcoin and Ethereum, which are prominent blockchain platforms, carry out 7 and 20 transactions per second, respectively. This is much less than popular platforms such as VISA, PayPal, and Amazon, which perform thousands of transactions per second. Therefore, this article presents comprehensive study of scalability improving techniques for blockchain and case studies for improving scalability by using some of the techniques. The scalability of blockchain systems can be enhanced by on-chain, off-chain, and machine learning algorithms. The proposed methodology improves the scalability using off-chain technique for supply chain management and KNN classification for the healthcare domain.
In the realm of cyber-physical systems, where tight integration between computational and physical elements is paramount, the demand for efficient and scalable machine learning models is ever-present. Bayesian Neural Networks (BNNs) present a promising avenue for tackling complex tasks in such systems, yet their widespread adoption is hindered by computational complexity and resource constraints. To address these challenges, we propose an energy-efficient FPGA implementation of Probabilistic Bayesian Neural Networks (ProbBNNs), a novel architecture that leverages probabilistic computing principles to streamline inference in BNNs. In ProbBNN, instead of representing each parameter as a random variable with a mean and variance, a set of parameters for each neuron is represented by a Probability Density Function (PDF) that characterizes the distribution of these random variables, with random streams following the PDFs processed through probabilistic computing principles to propagate uncertainty throughout the network. The adoption of probabilistic computing eliminates the need for expensive Multiply-Accumulate (MAC) operations, further enhancing the scalability and cost-effectiveness of our proposed implementation of ProbBNN in real-world applications. Furthermore, Gaussian Mixture Models (GMMs) are employed to efficiently capture the underlying distributions of weights, thereby reducing the number of BNN parameters. Through evaluation and comparison with traditional BNN architectures, this implementation demonstrates significant improvements in computational efficiency, memory utilization, and energy efficiency, making it well suited for deployment in resource-constrained cyber-physical systems, where efficient and reliable decision-making is crucial.
This article presents an AI-enabled Personalization Management (AIIM) software for human-in-the-loop, human-in-the-plant learning-enabled systems (LES). AIIM can be integrated with LES software to aid a human user in achieving safe and effective operation under dynamically changing contexts. AIIM consists of: (a) an AI technique to derive model coefficient of a physics-guided surrogate model from operational data shared following privacy norms, and (b) continuous model conformance to identify key changes in LES operational behavior that may jeopardize safety. We demonstrate two capabilities of AIIM, personalization and unknown error detection, through case studies that span a significant breadth of dynamic context change scenarios including (a) involuntary change in user context such as medication-induced glucose metabolism change in automated insulin delivery (AID), (b) actuation failure such as cartridge blockage in AID, (c) latent sensor error in aviation, and (d) unknown coding error in autonomous car software patches. We compare AIIM personalization with human-in-the-loop and self-adaptive model-predictive control design in real-life and simulation settings, to show safe and improved diabetes management.
The Field Programmable Gate Array (FPGA) market has seen significant growth due to the low cost and reduced time to market when compared to ASIC circuits. However, FPGAs' reconfigurable nature introduces security vulnerabilities that can be exploited by adversaries to obtain sensitive information. Physical Unclonable Functions (PUFs) have shown to be valuable security primitives. By leveraging manufacturing variations in a device, one can generate unique signatures that can be used for authentication and generation of secret keys. However, PUF implementation can be costly, taking up FPGA resources and requiring long design times. In this article, we propose a method which takes advantage of the FPGA look-up table (LUT) architecture to embed the PUF into functional logic circuits, reducing the cost and design time. We provide detailed implementation guidelines and evaluate the PUF's signature quality and stability under different environmental variations using a set of test-bench circuits. Our results demonstrate the effectiveness of our method in securing FPGA designs while reducing implementation costs and design time.
The modern semiconductor industry requires memory solutions that can keep pace with the high-speed demands of high-performance computing. Embedded non-volatile memories (eNVMs) address these requirements by offering faster access to stored data at an improved computational throughput and efficiency. Furthermore, these technologies offer numerous appealing features, including limited area-energy-runtime budget and data retention capabilities. Among these, the data retention feature of eNVMs has garnered particular interest within the semiconductor community. Although this property allows eNVMs to retain data even in the absence of a continuous power supply, it also introduces some vulnerabilities, prompting security concerns. These concerns have sparked increased interest in examining the broader security implications associated with eNVM technologies. This paper examines the security aspects of eNVMs by discussing the reasons for vulnerabilities in specific memories from an architectural point of view. Additionally, this paper extensively reviews eNVM-based security primitives, such as physically unclonable functions and true random number generators, as well as techniques like logic obfuscation. The paper also explores a broad spectrum of security threats to eNVMs, including physical attacks such as side-channel attacks, fault injection, and probing, as well as logical threats like information leakage, denial-of-service, and thermal attacks. Finally, the paper presents a study of publication trends in the eNVM domain since the early 2000s, reflecting the rising momentum and research activity in this field.
With concerns about data privacy growing in a connected world, cryptography researchers have focused on fully homomorphic encryption (FHE) for promising machine learning as a service solution. Recent advancements have lowered the computational cost by several orders of magnitude, but the latency of fully homomorphic neural networks remains a barrier to adoption. This work proposes using multi-exit neural networks (MENNs) to accelerate the FHE inference. MENNs are network architectures that provide several exit points along the depth of the network. This approach allows users to employ results from any exit and terminate the computation early, saving both time and power. First, this work weighs the latency, communication, accuracy, and computational resource benefits of running FHE-based MENN inference. We show FHE-MENNs improvement over single-exit networks on the accuracy-latency Pareto frontier, achieving around 7% accuracy boost for similar latencies. Then, we present the TorMENNt attack that can exploit the user’s early termination decision to launch a concrete side-channel on both plaintext and FHE-encrypted MENNs. In particular, we show that this attack leaks less than one bit per image per exit, and we demonstrate that TorMENNt can still infer private classification outputs. Results on a single CIFAR-10 image show that TorMENNt doubles an attacker’s likelihood of correctly predicting the user’s image class compared to random guessing, and on a batch of 100 images can achieve up to 68% prediction accuracy. We discuss possible countermeasures to mitigate the attack and examine their effectiveness. Finally, we tie the privacy risks with a cost-benefit analysis to obtain a practical roadmap for FHE-based MENN adoption.
The modelling of memristive devices is an essential part of the development of novel in-memory computing systems. Models are needed to enable the accurate and efficient simulation of memristor device characteristics, for purposes of testing the performance of the devices or the feasibility of their use in future neuromorphic and in-memory computing architectures. The consideration of memristor non-idealities is an essential part of any modelling approach. The nature of the deviation of memristive devices from their initial state, particularly at ambient temperature and in the absence of a stimulating voltage, is of key interest, as it dictates their reliability as information storage media—a property that is of importance for both traditional storage and neuromorphic applications. In this article, we investigate the use of a generative modelling approach for the simulation of the delay and initial resistance-conditioned resistive drift distribution of memristive devices. We introduce a data normalisation scheme and a novel training technique to allow the model to be conditioned on the continuous inputs. The proposed generative modelling approach is suited for use in end-to-end training and device modelling scenarios, including learned data storage, due to its differentiability and ability to generate target-delay samples without recurrent evaluation.
The increasing advancement of emerging device technologies that provide alternative basis logic sets necessitates the exploration of innovative logic design automation methodologies. Specifically, emerging computing architectures based on the memristor and the bilayer avalanche spin-diode offer non-commutative or `asymmetric' operations, namely the inverted-input AND (IAND) and implication as basis logic gates. Existing logic design techniques inadequately leverage the unique characteristics of asymmetric logic functions resulting in insufficiently optimized logic circuits. This paper presents a complete Boolean algebraic framework specifically tailored to asymmetric logic functions, introducing fundamental identities, theorems and canonical normal forms that lay the groundwork for efficient synthesis and minimization of such logic circuits without relying on conventional Boolean algebra. Further, this paper establishes a logical relationship between implication and IAND operations. A previously proposed modified Karnaugh map method based on a subset of the presented algebraic principles demonstrated a 28 computational steps for an algorithmically designed memristive full adder; the presently-proposed algebraic framework lays the foundation for much greater future improvements.
Multi-tenant Field-programmable Gate Arrays (FPGAs) in cloud service are vulnerable to remotely exploitable attacks, among which power waster circuit (PWC)-based fault attacks have been demonstrated as a highly feasible one. PWC generates high switching activities and causes a sudden voltage drop in the power distribution network (PDN), resulting in a delay of signal propagation and FPGA malfunction. Existing countermeasures deploy bitstream checking methodologies or deploy numerous on-chip sensors to mitigate voltage-drop attacks. Since new PWCs without combinatorial loops and a multi-source attack are emerging, the current countermeasures lack the ability to mitigate new security challenges in multi-tenant FPGAs. To address these issues, a Signal-slowdown (SS)-based fault attack mitigation (S 2 FAM) method is proposed to detect both combinatorial (ring-oscillator (RO)-based PWC) and non-combinatorial (ring-oscillator Flip-flop (ROFF)-based PWC) loop-based attacks and precisely pinpoint the attack locations. A new calibration technique in S 2 FAM facilitates to identify and remove unstable sensor data, thus significantly reducing false positives. Moreover, the proposed method localizes both the single- and multi-source attacks in the FPGA by utilizing a tenant-level SS ranking (TSSR)-based algorithm. Experimental results show that the proposed method reduces the false alarm by 45.8%, compared to the existing works. Our proposed algorithm for attack localization achieves a 100% success rate and reduces the attack localization area for a multi-source attack by 25.2% than an existing countermeasure. The successful localization is achieved by utilizing our proposed method within 2 \(\mu\) s (200 clock cycles) of attack duration. The proposed signal slowdown metric with the calibration process reduces the number of on-chip sensors by 78% and the localization time by 90.5%, compared to the baseline.
