The rapid growth of AI applications in real-time systems has heightened the demand for efficient acceleration techniques for convolutional neural network (CNN) inference. Field-programmable gate arrays (FPGAs) have emerged as a promising solution due to their energy efficiency and predictable timing behavior. Among various FPGA-based designs, the Deep Learning Processor Unit (DPU) released by Xilinx has become a popular choice for accelerating CNN inference. However, the standard toolchain for the Xilinx DPU supports only the deployment of homogeneous DPU architectures, which limits flexibility and resource utilization for multi-task workloads. This paper introduces RT-DPU, a systematic approach for the automated deployment of heterogeneous multi-DPU engines on FPGAs. Our method aims to meet real-time deadlines for a set of CNN inference tasks while minimizing FPGA fabric resource consumption. First, we develop a performance model that captures the combined impact of DPU compute capacity, resource usage, and CNN model characteristics. Based on this model, we propose a heuristic-based scheduling algorithm that partitions CNN tasks into segments and maps them to appropriate DPUs, reducing response times and balancing utilization. We further introduce an automated architecture selection algorithm to identify the optimal mix of heterogeneous DPU types for a given workload. We evaluate RT-DPU on a Xilinx ZCU102 platform. Experimental results demonstrate that RT-DPU consistently meets all task deadlines while reducing BRAM consumption by up to 34.6% compared to conventional homogeneous DPU baselines. Moreover, RT-DPU successfully schedules task sets that homogeneous deployments fail to complete within their timing constraints.

Worst-Case Execution Time (WCET) analysis provides an upper bound on a program’s execution time and is fundamental to the design and verification of real-time systems. Accurate modeling of cache behavior is critical for WCET estimation, as cache-miss latency is typically orders of magnitude larger than cache-hit latency. Since cache behavior is path dependent, existing methods commonly use abstract interpretation to estimate cache behaviors without enumerating all paths. However, conventional abstract interpretation is context-agnostic—adopting the most conservative case across paths—and thus may produce an overestimated WCET bound. To bridge the gap between scalability and accuracy, we propose a path-sensitive abstract-interpretation-based cache analysis that maintains a set of cache states drawn from critical execution paths to derive context-aware cache behavior. This path-sensitive cache analysis integrates seamlessly into standard WCET frameworks, resulting in tight yet provably sound WCET bounds. Experiments show that our approach improves WCET accuracy by an average of 24.83% without sacrificing scalability.

Log-structured merge (LSM) tree-based key-value (KV) stores organize writes into hierarchical batches to optimize write performance. However, the notorious compaction process and multilevel query mechanism of LSM-tree severely hurt system performance. Our preliminary experiments show that 1) When compaction occurs in the L0 and L1 of the LSMtree, it may saturate system computation and memory resources, ultimately causing the entire system to stall and 2) large number of iterative retrievals across multiple levels is usually required to locate the queried data, while redundant key range overlap in L0 further increases the overhead. Based on these observations, we introduce Re-LSM+, a resistive random-access memory (ReRAM)-based Processing-in-Memory framework for LSMbased KV Stores. In Re-LSM+, we offload compaction tasks from the higher levels of the LSM-tree to the PIM processing part. A highly parallel ReRAM compaction accelerator is designed by breaking down the three-phase compaction process into basic logic operations. Additionally, we design an index table and a multilayer Bloom filter for different levels to improve the query efficiency of the LSM-tree. Evaluation results from db_bench show that Re-LSM+ achieves a 2.37x improvement in random write throughput compared to RocksDB. Furthermore, the ReRAM-based compaction accelerator achieves a 68.16x speedup over the CPU-based implementation and reduces energy consumption to 25.5x.

Zero-knowledge proofs (ZKPs) are cryptographic protocols that allow verification of statements without disclosing the underlying information. Among them, PLONK-based ZKPs are particularly notable for offering succinct, non-interactive proofs of knowledge with a universal trusted setup, leading to widespread adoption in blockchain and cryptocurrency applications. Nonetheless, their broader deployment is hindered by long proof-generation times and substantial memory demands. While GPUs can accelerate these computations, their limited memory capacity introduces significant challenges for efficient end-to-end proof generation. This paper presents Pipelonk, a GPU-accelerated framework for end-to-end PLONK proof generation with two key contributions. First, Pipelonk introduces a segmentable operator library that offloads all operations, including those not trivially parallelized, to GPUs through new designs. Each operator supports segmented execution, allowing inputs to be divided into smaller segments processed independently, thus enabling large-scale computations on memory-constrained devices. Second, Pipelonk provides a pipeline executor that overlaps computation and data transfer. It globally schedules compute- and memory-intensive tasks while preserving data and security dependencies, balances transfer-latency hiding against peak memory, and adaptively selects per-operator segment sizes by modeling memory capacity and computational characteristics to maximize compute-transfer overlap. Evaluation shows that Pipelonk runs efficiently on devices with 8 GB to 80 GB memory, achieving an average speedup of 10.7x and up to 19.4x over the state-of-the-art baseline.

Homomorphic Encryption (HE)-based Private Information Retrieval (PIR) allows clients to retrieve plaintext records from untrusted servers without revealing query content. While promising in theory, existing solutions fall short in practice due to two fundamental limitations: (1) poor support for dynamic datasets, which limits applicability in real-world, evolving workloads; and (2) excessive I/O overhead from full-database scans. These bottlenecks prevent current designs from bridging the gap between cryptographic privacy and system efficiency. In this paper, we introduce Conflux, an efficient keyword PIR system for dynamic data environments through a protocol-architecture co-design approach. At the protocol level, Conflux employs a novel two-phase retrieval mechanism, consisting of an oblivious filtering phase followed by a precise retrieval phase. This design natively supports efficient online insertions, deletions, and updates, while maintaining near-optimal computational complexity. At the system level, Conflux adopts a heterogeneous accelerator architecture that tightly couples computational storage devices and incorporates software-hardware co-optimization techniques to mitigate I/O bottlenecks. Experimental results show that Conflux reduces query processing time by up to 2.64x compared to the state-of-the-art methods, while retaining full support for dynamic datasets.

Static worst-case execution time (WCET) analysis is crucial for designing safety-critical real-time systems, as it provides an upper bound on the execution time of real-time applications on the underlying hardware. While digital signal processors (DSPs) are widely adopted in real-time systems due to their specialized architecture, optimized instruction set, power efficiency, and real-time processing capabilities, existing WCET analyses primarily focus on general-purpose CPU cores, with limited attention given to DSPs. This paper addresses this gap by proposing a WCET analysis tool called Xihe for DSPs. Xihe introduces a timing semantics to precisely model control-flow among instructions and presents novel techniques for constructing the control-flow graph and detecting loop bounds based on these semantics. Additionally, a novel memory access behavior analysis which takes into account the DSP's instruction-level parallelism execution flow is developed. Experimental evaluation of Xihe using MRTC benchmark programs on the C66x core demonstrates a relatively tight average overestimation of 67% compared to measured results.

Keyword Private Information Retrieval (PIR) systems that leverage Homomorphic Encryption (HE) allow for the execution of private queries on public databases hosted by untrusted servers. However, existing solutions are significantly hindered by high computational overhead and inefficiencies in handling variable-length data, which impose limitations on their practical deployment. To address these challenges, we propose PIRacle, a high-performance protocol and deployment-optimized private retrieval system for key-value stores. First, PIRacle introduces a lightweight computational protocol that substantially reduces computational overhead by utilizing constant-weight codes and Fermat's Little Theorem. Additionally, to address the inefficiencies associated with variable-length data, PIRacle applies a two-pass sorting strategy combined with computation pruning, effectively mitigating the computational expansion typically induced by padding overhead in conventional designs. Moreover, PIRacle incorporates a workload-aware scheduling framework that dynamically distributes computation across parallel execution units, enabling efficient scaling with available hardware resources. Experimental results demonstrate that PIRacle reduces server-side latency by up to 88.5 & times; compared to the state-of-the-art solution.

This paper presents a hardware/software (HW/SW) co-designed Module-Lattice-based Key-Encapsulation Mechanism (ML-KEM) accelerator featuring an ARM processor for runtime scheduling and a reconfigurable FPGA for efficient cryptographic kernel execution. Our design supports seamless, bitstream-free switching among ML-KEM's three security levels (1/3/5), enabling real-time key generation, encapsulation, and decapsulation. We propose a Preprocessed Multi-path Delay Commutator NTT (PMDC-NTT) architecture, achieving 15.4% logic reduction and 14.2% latency improvement over conventional MDC-NTT. The proposed HW/SW co-design achieves over 6.7x speedup through pipelined task parallelism, demonstrating significant advantages in both performance and flexibility over prior works.

In the context of cloud computing, services are held on cloud servers, where the clients send their data to the server and obtain the results returned by server. However, the computation, data and results are prone to tampering due to the vulnerabilities on the server side. Thus, verifying the integrity of computation is important in the client-server setting. The cryptographic method known as Zero-Knowledge Proof (ZKP) is renowned for facilitating private and verifiable computing. ZKP allows the client to validate that the results from the server are computed correctly without violating the privacy of the server's intellectual property. Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zkSNARKs), in particular, has been widely applied in various applications like blockchain and verifiable machine learning. Despite their popularity, existing zkSNARKs approaches remain highly computationally intensive. For instance, even basic operations like matrix multiplication require an extensive number of constraints, resulting in significant overhead. In addressing this challenge, we introduce zkVC, which optimizes the ZKP computation for matrix multiplication, enabling rapid proof generation on the server side and efficient verification on the client side. zkVC integrates optimized ZKP modules, such as Constraint-reduced Polynomial Circuit (CRPC) and Prefix-Sum Query (PSQ), collectively yielding a more than 12-fold increase in proof speed over prior methods. The code is available at https://github.com/UCF-Lou-Lab-PET/zkformer

Zero-knowledge proofs validate statements without revealing any information, pivotal for applications such as verifiable outsourcing and digital currencies. However, their broad adoption is limited by the prolonged proof generation times, mainly due to two operations: Multi-Scalar Multiplication (MSM) and Number Theoretic Transform (NTT). While MSM has been efficiently accelerated using multi-GPU systems, NTT has not, due to the high inter-GPU communication overhead incurred by its permutation data access pattern. This paper identifies the necessity of multi-GPU NTT support for end-to-end proof generation. It introduces UniNTT, an NTT algorithm tailored for multi-GPU systems. The data access pattern of NTT incurs communication across all levels of the multi-GPU hierarchy (i.e., warp, thread block, GPU, and multi-GPU), complicating the implementation of multi-GPU NTT. To this end, UniNTT proposes a novel, overheadfree decomposition approach that recursively decomposes an NTT into smaller NTTs, enabling all hierarchy levels execute the same NTT computations at different scales. It promotes a uniform design of NTT optimizations based on an abstract hardware model, which are then tailored and applied to different levels of the hierarchy. UniNTT not only simplifies the optimization process but also shows that optimizations typically specific to one level can also be effectively generalized to others. Experiments show that UniNTT achieves an average 4.26x speedup compared to leading NTT implementations when both are executed on an 8-GPU system.

Large transformer-based models have achieved remarkable performance in natural language processing and related fields, yet they pose significant privacy risks when handling sensitive data. Fully homomorphic encryption (FHE) offers a natural solution for private transformer inference: the client encrypts the input data, the server performs inference directly on ciphertexts, and the results remain encrypted until decrypted by the key holder. However, FHE struggles to efficiently support non-linear activation functions, and encrypted inference often incurs substantial performance overhead and degrades model accuracy. To address these challenges, we propose Hamster, an FHE-based private transformer inference system that protects both client and server privacy. Our contributions are twofold. First, Hamster introduces a comprehensive set of more efficient approximations for the costly nonlinear functions in transformer models, significantly reducing the performance overhead of homomorphic evaluation. Second, unlike some existing works that only support a limited set of nonlinear components, Hamster implements a complete end-to-end evaluation pipeline for private transformer inference. Extensive experiments demonstrate Hamster achieves an average inference time of approximately 12 minutes per token, with minimal loss in model accuracy. This performance outperforms BumbleBee (NDSS 2025) by 2.2x and NEXUS (NDSS 2025) by 1.2x, highlighting the effectiveness and practicality of our system.

Embedded real-time systems are increasingly turning to GPU-based SoCs to efficiently handle machine learning tasks at the edge. Modern GPU SoCs often feature specialized AI accelerators to enable concurrent CNN inference while maintaining energy efficiency. While this trend typically leads to a general improvement in performance, the integration of multiple AI accelerators presents challenges for building real-time systems, where ensuring timing predictability is a key design goal. On one hand, contention among various computation units over shared memory can introduce non-deterministic timing behaviors. On the other hand, the built-in GPU scheduling mechanism cannot assure that emergent tasks to be executed first, potentially violating real-time constraints. To tackle these challenges, this study introduces a timing predictability-aware cache locking policy to reduce main memory access volume and mitigate main memory contention with AI accelerators. Additionally, a real-time scheduling framework is proposed to bypass the inherent GPU scheduling algorithm.

In enormous privacy-sensitive machine learning application domains with collaborative data acquisition from multiple participants, secure multi-party computation (MPC) becomes a promising solution for privacy-preserving machine learning (PPML). Secret sharing protocols is a prevalent MPC strategy, where frequent data distribution and recombination are applied to uphold the confidentiality of participants' data. A key challenge for practical deployment of secret sharing protocols in PPML is the massive and unbalanced computation and communication workloads occurred in various linear and non-linear stages of machine learning. The imbalance could be further amplified when powerful hardware accelerators are designed to reduce the computation latency. In this work, we propose Co-Prime, an FPGA-based 3PC framework for efficient PPML without assistance from a secure third party. Co-Prime integrates protocol and hardware co-optimizations to mitigate the communication bottlenecks in secret sharing schemes. Particularly, Co-Prime proposes a novel protocol conversion technique that seamlessly converts data formats to adaptively adopt preferred protocols in various stages of PPML. Accelerator-friendly MPC primitives and system-level design space exploration schemes are designed to achieve latency hiding through overlapping computation and network communication. Finally, it enables direct interaction with data streams via network communication modules on FPGAs to further reduce the network communication overhead. Experimental results demonstrate significant performance improvements over existing privacy-preserving machine learning frameworks, with 2-18x speedup in inference latency across various LAN/WAN environments and neural network models.

Fully Homomorphic Encryption-based Private Information Retrieval systems provide strong privacy by enabling encrypted queries on databases hosted by untrusted servers. However, adoption is limited by system-level bottlenecks, including severe I/O constraints in large-scale settings and inefficiencies in handling variable-length data. To solve these issues, we present SmartPIR, a scalable PIR system that tackles these challenges through a protocol and architecture co-design. First, we introduce an in-storage computing framework that offloads FHE operations to computational storage devices (CSDs), eliminating the overhead of large-volume data movement. To address the limited computational capacity of CSDs, we further propose a zero-skipping encoding strategy at the protocol level, which decouples actual payloads from paddings to avoid redundant computations. Additionally, SmartPIR incorporates two key architectural optimizations: (1) a resource-efficient FPGA circuit design and (2) a load-aware scheduling strategy, which collectively sustain high throughput and ensure scalability. Implemented on a commercial off-the-shelf CSD array, SmartPIR achieves a 10(2) x +/- 10(3) x speedup over state-of-the-art CPU-based PIR schemes.

The Deep Learning Processor Unit (DPU) released in the official Xilinx Vitis AI toolchain stands as a commercial off-the-shelf solution tailored for accelerating convolutional neural network (CNN) inference on Xilinx FPGA devices. While most FPGA accelerator focus on high performance and energy-efficiency, analyzing the worst-case execution time (WCET) bound is essential for using CNN accelerations in real-time embedded systems design. In this work, we show that in a multi-DPU environment, the observed worst-case inference time for a CNN inference task could become 3X larger w.r.t. the best case inference time, which prompts the prominent importance of a static timing analysis for FPGA-based CNN inference. We propose, to the best of the authors' knowledge, the first static timing analysis framework for CNN inference in a multi-DPU environment. The proposed framework introduces a generalized timing behavior model for shared bus arbitration and memory access contention between parallel running DPU engines. Additionally, it incorporates a fine-grained memory access contention analysis that takes into account the characteristics of deep learning applications. For a single-DPU environment, the analysis result is 27% tighter in average compared with the state-of-the-art results. Furthermore, our proposed method produces relatively tight estimated results in the multi-DPU environment.

While homomorphic encryption (HE) has been well-recognized as a promising data privacy protection technique, there are many challenges to the real-world deployment of HE applications. In this work, we propose a design flow for parameter-adaptive and memory-efficient FPGA acceleration of homomorphic encryption. In the framework, we explore the correlations between HE parameter selection to meet various design objectives and the huge design space due to underlying FPGA hardware resource allocation. Particularly, we demonstrate that adaptive management of the FPGA memory hierarchy is crucial to supporting diverse cryptosystem parameter selection for application-level security, accuracy, and performance requirements. We propose a resource-efficient and flexible micro-architectural design for HE operations, where data access patterns in various pipeline execution stages are optimized for high memory bandwidth utilization. Furthermore, a memory-aware performance model is built for automatic design space exploration for cryptosystem parameter selection and hardware resource provisioning. Experimental results show 1.50X and 1.16X speedup for the NTT and Rotation operations w.r.t. the state-of-the-art FPGA implementation. Meanwhile, the proposed framework generates flexible and high-performance accelerator code for real HE application kernels with different cryptosystem parameters on a wide range of FPGA devices.

To address the growing security issues faced by ARM-based mobile devices today, TrustZone was adopted to provide a trusted execution environment (TEE) to protect sensitive data. Such TrustZone-based models have been proven to be effective, but they target CPU architectures and do not work for the security of widely used heterogeneous computing platforms such as FPGAs. To solve this issue, we propose a comprehensive SoC-FPGA security framework, FPGA-TrustZone, to support FPGA TEE by extending the security of ARM TrustZone. Experiments on real SoC-FPGA hardware development boards show that FPGA-TrustZone provides high security with low performance overhead.

High-precision integer multiplication is crucial in privacy-preserving computational techniques but poses acceleration challenges on GPUs due to its complexity and the diverse bit lengths in cryptosystems. This paper introduces GIM, an efficient high-precision integer multiplication algorithm accelerated with GPUs. It employs a novel segmented integer multiplication algorithm that separates implementation details from bit length, facilitating code optimizations. We also present a computation diagram to analyze parallelization strategies, leading to a series of enhancements. Experiments demonstrate that this approach achieves a 4.47× speedup over the commonly used baseline.