Multi-level-cell (MLC) resistive random-access memory (RRAM) promises superior computational density and energy efficiency for compute-in-memory (CIM) systems, yet its potential is limited by analog RRAM instability and the power-hungry bitline (BL) regulation amplifiers in prior Ohm's-law-based designs. We demonstrate a 180-nm CIM macro with process-optimized back-end-of-line (BEOL) HfO2 MLC RRAM. The devices exhibit stable 3-bit conductance states (<9.8% deviation), 10(4 )-cycle endurance, and 10(4)-s retention at 85 degrees C. At the circuit level, a BL regulation-free analog MAC scheme combined with a bit-masked multi-bit input method eliminates column-wise BL-regulation amplifiers and input-bit-significance recovery. This enables direct-current-free computation, reducing per-column power by >74%. Silicon measurements of the 180-nm prototype deliver a peak energy (area) efficiency of 819 TOPS/W/bit (1.115 TOPS/mm(2)/bit). Furthermore, post-layout simulations of a 22-nm implementation project 14,123 TOPS/W/bit and 412.2 TOPS/mm(2)/bit, respectively.

The escalating demand for high-performance computing has spurred interest in integrated silicon photonics to overcome the constraints of traditional von Neumann architectures. Reconfigurable photonic devices with low optical loss, high-speed switching, and nonvolatile operation are essential especially for photonic neural networks. This study introduces a robust high-throughput methodology that serves as a primary engine for accelerating compositional search within the ternary Ge-Sb-Te (GST) system. Through this approach, we unveiled Ge3Sb2Te15 (GST3215), a novel optical phase-change material (OPCM) that mitigates the high optical losses inherent in conventional OPCMs like Ge2Sb2Te5 (GST225). With reduced extinction coefficients and an improved figure of merit, GST3215 seamlessly integrates into hybrid silicon micro-ring resonator (MRR), achieving lower insertion loss, a broader modulation range, and precise multilevel optical modulation-ideal traits for reconfigurable photonic systems. Moreover, GST3215 supports programmable nonlinear activation functions (e.g., ReLU, ELU, RBF) in a photonic neural network, lifting classification accuracy on the FashionMNIST dataset from 84.5% to 87.7%. These findings position GST3215 as a game-changer for large-scale photonic integration and optical computing.

This work presents a fully analog intelligent vision SoC that eliminates both sensor-processor and inter-layer A/D conversions for end-to-end vision. A continuous analog datapath from sensing to multi-layer inference is enabled by a PWM imager, an RRAM- based CIM, and a linearity-recovery analog memory. Fabricated in 55nm CMOS, the chip achieves 11pJ/(pixel center dot frame) sensing efficiency, 8,791 TOPS/W MAC efficiency, and 346 TOPS/W system-level efficiency across diverse vision tasks.

Understanding the contact resistance (RC) of back-end-of-line (BEOL) compatible oxide thin-film transistors (TFTs) is critical for drive current optimization especially in advanced technology node. Here, we elucidate the contributions of RC in an indium–gallium–zinc oxide (IGZO) TFT by integrating the transfer length method (TLM) and contact-end-resistance (CER) model, supported by physical and material characterization of the TFT, where RC is divided into the Schottky barrier resistance (RSC), the effective interlayer resistance (RInt), and the resistance of IGZO beneath the contacts (RIGZO). Using our fabricated IGZO TFT as a test vehicle, we show that the RIGZO represents around two-third of the total RC and a significant one-third contributed by the interfacial contact layer, with a negligible RSC. By decomposing the RC components, they can be separately addressed for device optimization, thus guiding device architecture or process design for future monolithic three-dimensional chip.

Multi-level-cell (MLC) resistive random-access memory (RRAM) has emerged as a promising candidate for high-density compute-in-memory and neuromorphic systems. However, the accuracy of MLC read operations is commonly degraded by process variations and parasitics, especially in time-based sensing schemes. This paper proposes a self-referenced time-based readout circuit for 3-bit MLC 1T1R RRAM arrays, featuring a replica bitline (RBL) calibration technique and a 3-bit interleaved Hamming-code-based error correction (ECC) scheme. The proposed RBL dynamically tracks parasitic delay and process variations, enabling accurate sensing without additional analog circuitry. Furthermore, the lightweight 3-bit ECC further enhances read reliability with minimal area overhead. Post-layout simulations in a 40-nm CMOS process show an improvement in read symbol-error ratio (SER) from 16.44% to 0.63% after replica calibration and to below 10-4 after ECC correction, with 0.22 pJ/bit energy consumption at a 9.2-ns read clock period and 1.2-V supply, demonstrating superior robustness and energy efficiency over prior RRAM readout schemes.

Bioelectronic implants have enabled precise and closed-loop interfacing with biological systems to diagnose, monitor, and treat disorders. A critical challenge for these chronically implanted systems is the design of a robust, real-time wireless data uplink and a continuous, efficient wireless power delivery link within a severely constrained form factor. Ultrasound, thanks to its advantageous path loss and safety limit, has become a promising medium. However, conventional ultrasound power and communication approaches either employ two separate transducers, resulting in a larger form factor or utilize pulse-echo backscatter with a single transducer, which suffers from time-multiplexed uplink transmission, limited data rate, and inefficient power delivery. This work introduces a single-transducer architecture that enables concurrent ultrasound power delivery and backscatter-based data communication, based on a unified impedance-based operating region that allows efficient downlink power harvesting and reliable uplink backscatter modulation simultaneously. The proposed single-stage power regulator modulates its input impedance via inductor charging-time control for data transmission while remaining decoupled from load variations, ensuring uninterrupted energy harvesting. The system further implements channel-adaptive modulation (BPSK, APSK, 4-ASK) to dynamically optimize the trade-off between data rate, reliability, and power delivery. Fabricated in 180 nm CMOS with a 0.28 mm(2) core area and validated in oil at 5 cm depth with a 1 MHz acoustic wave, the system enables real-time data transmission and the highest spectral efficiency of 300 kbps/MHz with a bit error rate (BER) below 10(-6) while achieving 192 & micro;W of continuous power delivery.

There are two general approaches in guiding intelligent vision system development: one emphasizes ultra-flexibility (reconfigurability) for adapting to various scenarios, and the other emphasizes ultrahigh power efficiency tailored to specific applications. The pinnacle design is geared toward the biological vision system with concurrent high levels of on-demand intelligence, efficiency, and flexibility. However, current state-of-the-art intelligent vision systems are far behind, relying on heterogeneously integrated and limited-function single devices, alongside rigid sensing/computing architecture, thus preventing flexibility for low area and power efficiency toward dynamic and unpredictable scenarios. This work bridges the neuromorphic gap with an on-demand ultra-reconfigurable vision system, demonstrating true reconfigurability across device, cell, array and system levels. This is enabled by a multi-paradigm device array capable of seamless switching between spiking, non-spiking, neuromorphic imaging (NI), and artificial intelligence (AI) computing modes, as well as a reconfigurable circuit and architecture design. The system is capable of on-demand allocating resources between NI and AI functionalities for high-quality smart imaging and high-accuracy recognition tasks, and transitioning between spiking and non-spiking modes for frameless dynamic and frame-based static scenarios. Superior power efficiencies of up to 52.6 TOPS/W for NI-centric computing and 75.5 TOPS/W for NI/AI hybrid computing are achieved, which are up to two orders of magnitude larger than the state-of-the-art intelligent vision system.

Edge-AI systems based on resistive random-access memory (RRAM) compute-in-memory (CIM) hardware suffer from conductance drift induced by intrinsic device non-idealities such as relaxation and read-disturb effects, leading to gradual degradation of inference accuracy. Existing calibration methods either reprogram all RRAM weights at the cost of endurance degradation or depend on off-chip retraining, preventing fully autonomous on-chip learning. This work presents an on-chip-integrable, zero-RRAM-write conductance drift calibration method that combines a low-rank-adaptation (LoRA)-based CIM architecture with a layer-wise distillation-based weight update scheme. The proposed approach reduces the number of updatable weights to below 5% and performs in-situ LoRA computation within the RRAM CIM array via pseudo-RRAM cells, eliminating RRAM rewriting and additional hardware overhead. It also eliminates cross-layer backpropagation and lowers the calibration dataset requirement to fewer than five samples, enabling low-cost on-chip self-calibration with a total area of 1.422 mm2 in 22 nm CMOS. Simulation results based on measured RRAM conductance drift data demonstrate that, using only 4 samples for calibration, the inference accuracy of ResNet-20 is recovered from 68.77% (46.41%) to 86.54% (62.06%) on CIFAR-10 (CIFAR-100) dataset.

This work presents a scalable Vision-Language-Action (VLA) edge processor for real-time robot control. A SimHashbased temporal token filtering eliminates redundant visualtoken computation across action steps, while a hybrid RRAMSRAM Processing-Near-Memory engine with compression and dynamic orchestration achieves zero external memory access. A 16-chip module in 55 nm achieves $6.7-\text{ms}$ perception-to-action latency (150 Hz) with 12.74 mJ energy, delivering a $1.87-88.45 \times$ latency reduction over prior art and demonstrating end-to-end VLA inference at the edge.

Logic-in-Memory (LiM) architecture uses its unique tunable memory states to realize different logic functions within a single cell, greatly improving its area efficiency. In this work, we propose a reconfigurable complementary oxide-based 1FeFET-1pFET (1F1P) LiM cell that supports 14 types of reconfigurable logic operations. Leveraging the complementary characteristics of FeFET and pFET devices, the proposed design achieves a low static power consumption down to 10.97 pW. Array-level Spectre simulation based on the 1F1P structure shows an energy efficiency of 74 TOPS/W for the INT4 MAC in ResNet-20 inference on the CIFAR-10 dataset with peak throughput of 671 GOPS, underscoring the potential of complementary 1F1P for next-generation low-power reconfigurable logic.

Low-temperature processable oxide-based devices provide a promising avenue to monolithic 3D (M3D) IC chips. Here, oxide-based complementary metal-oxide-semiconductor (CMOS) logic circuits consisting of M3D stacked field effect transistors (FETs) - SnOx p-FET at the bottom and IGZO n-FET at the top are reported. By controlling the deposition process and keeping the entire fabrication thermal budget below 250 degrees C suitable for BEOL integration process, excellent uniformity and matched threshold voltage (V-th) of 0.5 V are achieved for both types of devices. As a result, minimally skewed operation of the stacked inverter is ensued, with voltage gain reaching a decently high value of 100.6 V/V at a V-DD of 1.5 V. Key logic gates utilizing the M3D stacked FETs including NAND, NOR, and SRAM cell were first demonstrated (SnOx p-FET based), showing robust and reliable logical functionality, together with a three-stage ring oscillator achieving a ringing frequency up to 62.5 kHz at a V-DD of 2.5 V.

Relatively few in-depth studies on MOSFET mobility are published at cryogenic temperatures partially due to lack of appropriate extraction method associated with more complicated scattering mechanisms than at room temperature. This paper, for the first time, proposes a new Y-function method, which is both physically and engineering novel, for mobility extraction considering the Coulomb scattering that dominates toward cryogenic temperatures. This new Y-function method demonstrates excellent fit with measurement data taken from foundry fabricated 180 nm bulk MOSFETs for the temperature range from 300 down to 4 K.

This work presents a fully analog intelligent vision SoC that eliminates both sensorprocessor and inter-layer A/D conversions for end-to-end vision. A continuous analog datapath from sensing to multi-layer inference is enabled by a PWM imager, an RRAM-based CIM, and a linearity-recovery analog memory. Fabricated in 55 nm CMOS, the chip achieves 11pJ/(pixel.frame) sensing efficiency, 8,791 TOPS/W MAC efficiency, and 346 TOPS/W system-level efficiency across diverse vision tasks.

Cryogenic CMOS (Cryo-CMOS) circuit design requires precise modeling of metal interconnect resistance and MOSFET behavior at cryogenic temperatures to ensure accurate performance predictions. Widely accepted industrial models, while effective at room temperature, fail to account for the unique physical mechanisms present in cryogenic conditions. This work establishes a cryogenic metal interconnect resistance simulation model based on experimental characterization of a 40-nm process down to 4 K. Additionally, a threshold voltage model is calibrated using cryogenic temperature measurements to capture MOSFET performance changes. These models are applied to analyze and predict the performance of an $LC$ oscillator under a 40-nm process, including its oscillation point, power consumption, and frequency. Experimental results validate the reliability of the proposed models, offering a comprehensive framework for Cryo-CMOS circuit design at cryogenic temperatures.

RRAM-based in-memory computing (IMC) offers high energy efficiency but suffers from conductance drift that severely degrades long-term accuracy. Existing approaches including retraining, noise-aware training, and Batch Normalization (BN)-based calibration either require RRAM rewriting, demand large storage overhead, or rely on online correction. We propose VeRA+, a lightweight drift compensation framework that reuses shared projection matrices and introduces only two compact drift-specific vectors per drift level. A drift-aware scheduling algorithm offline-trains a small set of VeRA+ parameters and selects the appropriate set over time without any on-chip retraining or data replay. VeRA+ preserves up to 99.77

The Posit number system has been introduced to enhance the decimal accuracy for values with small exponents by adopting a nonuniform dynamic range and precision, as opposed to the conventional IEEE-754 floating-point (FP) number system that imposes uniform accuracy across a wide range of exponents. However, conventional FP-only or Posit-only number systems exhibit computational inefficiencies and accuracy constraints: 1) dynamic timing slack (DTS) arising from unused mantissa bits remains unexploited; 2) accuracy is affected by the range of data magnitudes. In this work, we propose: 1) a run-time bitwidth-based adaptive clocking for throughput improvement by exploiting the DTS based on run-time mantissa bitwidth; 2) a mixed Posit-FP number system supporting additional accuracy-oriented and performance-oriented mixed data formats. Measurement results on a 40-nm test chip show that up to 79.6% throughput improvement is achieved by the proposed bitwidth-based adaptive clocking scheme at only 2.2% area overhead. Additionally, the mixed Posit-FP number system can maintain either the highest throughput or the highest accuracy across a wide numerical magnitude range of $10^{-30}\sim 10^{30}$ .

Recent advances in computer vision (CV) have introduced a variety of neural network (NN) architectures, including convolutional neural networks (CNNs), vision Transformers, and hybrid CNN-Transformer models. These models involve operators with widely varying computation and memory access patterns, demanding highly flexible and adaptive hardware for efficient execution. However, prior vision accelerators typically adopt fixed, one-size-fits-all designs, leading to inefficient hardware utilization under such diversity. In this work, we propose AdaPIM, an adaptive compute-in-memory (CIM) accelerator that dynamically reconfigures hardware resources to match the varying computation and memory characteristics of diverse CV workloads. AdaPIM incorporates: 1) a reconfigurable 4D-CIM processor that enables adaptive inter-macro parallelism along four architectural dimensions to improve spatial utilization under diverse computation patterns; 2) a flexible on-chip memory system that supports adaptive feature reuse at both register and global buffer levels to reduce on-/off-chip memory traffic under varying access patterns; and 3) a high-throughput vector core optimized for Softmax and layer normalization (LN) through algorithm-architecture co-design. Fabricated in 22nm, AdaPIM achieves chip-level energy efficiency of 22.7-63.9TOPS/W and system-level latency [including external memory access (EMA)] of 1.87-17.16 ms/frame with hardware utilization up to 83.12%, delivering improvements of 1.09- 13.96x in frame rate and 1.76- 3.41x in utilization, respectively, over state-of-the-art accelerators across diverse vision workloads.

Memtransistors, three-terminal devices that combine the functionalities of memristors and transistors, offer a promising route for analog computing through their non-volatile behavior, low power consumption, and gate-tunable control. These features make them particularly well-suited for sensor fusion in autonomous systems. However, such tasks are typically implemented using digital Kalman filters, which suffer from high power consumption and limited real-time adaptability due to analog-to-digital conversion and iterative computation. Existing analog approaches based on memristors also fall short in handling multi-dimensional data under complex driving scenarios. To overcome these challenges, an analog multi-stage Kalman filtering system integrated with MoS2 memtransistors is presented, designed for multi-dimensional sensor data in autonomous driving. The three-terminal memtransistor enables multi-level conductance (1024) and excellent electrostatic control. This ensures a wide modulation range (>103) and exceptional linearity (R2 = 0.997) for Kalman gain (K), facilitating robust adaptation to complex driving conditions. The proposed system effectively handles sensor obstructions while achieving a 13-fold reduction in power consumption and a 59-fold decrease in latency compared to conventional digital circuits. These results demonstrate the potential of memtransistor-based analog computing for real-time, energy-efficient sensor fusion in next-generation autonomous systems.

Optical phase-change materials (OPCMs) are promising nonvolatile tuning media for photonic integrated circuits, yet at telecom wavelengths their practical use remains constrained by the trade-off between refractive-index modulation and optical absorption. Here, we establish a high-throughput combinatorial library across the Ge-Sb-Te-S-Se quinary compositional space and construct composition-optical constant maps that reveal device-relevant compositional windows for simultaneously targeting strong index modulation and low loss. At 1550 nm, the maps identify a high-contrast window (Delta n approximate to 1.5-1.7, k c approximate to 0.13-0.27) and a low-loss window (k c approximate to 0-0.06 with Delta n approximate to 0.9-1.2), thereby enabling application-oriented materials selection. From the high-contrast window, we select Ge14.6Sb29.4Se35.3S11.3Te9.4 (GSSST-1), which switches at 1550 nm from (n, k) = (3.099, similar to 0) to (4.721, 0.227). When integrated into hybrid silicon microring resonators (MRR), GSSST-1 yields a crystalline propagation loss of 0.282 dB/mu m, corresponding to an similar to 26.9 & times; reduction relative to a same-thickness GST225 top-cladded MRR, while supporting 22 distinguishable intermediate states. Moreover, under single-wavelength readout, multilevel state programming enables five nonlinear transfer functions from the same device (ReLU, Softplus, ELU, RBF, and Half-sigmoid), which improve FashionMNIST classification performance relative to a linear baseline. Overall, this work connects high-throughput materials discovery with resonator-level benchmarking and programmable nonlinear photonic functionality, providing a materials-device codesign basis for low-loss OPCMs in scalable integrated photonic computing and reconfigurable circuits.

Investigating low-temperature logic technology (LTLT) down to milli-Kelvin temperatures is crucial for exploring fundamental cryogenic CMOS performance limits and supporting cryogenic control circuits for quantum computing. This paper, for the first time, systematically investigate overall MOSFET performance tailored for mK operation. MOSFETs fabricated by a leading foundry are characterized and modeled down to 9mK. Key device parameters of subthreshold swing (SS), mobility, threshold voltage (Vth), effective channel length (Leff) and parasitic series resistance (RSD) that are defined by physical effects are investigated. A new set of scalable insights for mK MOSFET devices and cryo-CMOS designs is provided.