Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.

In this work, the optimum design of Trigate-on-Insulator MOSFET devices is investigated with the MASTAR platform, focusing on the channel aspect ratio. First, the MAS-TAR Trigate model is described, and new components are validated with TCAD simulations. Using the verilog-A implementation of this model, SPICE simulations of inverter chains are later performed to analyze the device performance, employing different power reduction techniques. Finally, the variability issue is addressed with Monte-Carlo simulations of 6T SRAM cells.