A high performance Ge FinFET CMOS invertor with $\mathrm{I}_{\text{ON}}=2\quad \text{mA}/\mu\mathrm{m}$ at $\mathrm{V}_{\text{OV}}\ =1\mathrm{V},\quad \mathrm{S}.\mathrm{S}.=64\quad \text{mV}/\text{dec}, \mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}}=2.5\times 10^{6}$, and voltage gain=90 V/V is achieved by a high pressure supercritical fluid hydroxide oxidation, due to the reduced unstable oxidation states and oxygen vacancy.
We propose a new single-electron (SE) circuit inspired by the principles of molecular computing. SE circuits can control individual electrons and have features such as stochastic operation and nonlinearity. However, an optimal information processing method has not been established yet. In contrast, molecular computing is being studied as an information-processing method using molecular reactions [1] . In the referenced molecular computing theory, the problem is solved by mapping the concentration of molecules to initial and steady states, the reaction rate of molecules to state transition probabilities, and for each state to the type of molecule (Fig. 1). By mapping the behavior exhibited by SE circuits to this model, we believe that a new SE information-processing circuit can be realized.
A 1kb macro of One Time Programming (OTP) memory, implemented by a novel architecture of a 2T PMOS structure, has been realized on a foundry pure logic 28nm HKMG CMOS platform. The feature size of a unit cell is 2T per cell with 0.04995um 2 . The experimental results show that the designed macro exhibits high programming (PGM) speed of 100ns at 4.6V, the read voltage can be smaller than 1.15V within smaller than 10ns of sense time, and excellent data retention under one-month baking at 150°C. More importantly, it demonstrated high endurance, immunity from the read and program disturbances, which is superior to the mainstream technologies of anti-fuse OTP. This OTP is also expected to be scalable to advanced node such as FinFET and provides an ideal and reliable solution for the hardware security in IoT and 5G era.
In this work, the Back-side Power Delivery Network (BSPDN) based on the NSFET and FINFET standard cell arrays are constructed for the thermal analysis in comparison of front-side power delivery networks (FSPDN). The performance metrics reflecting the IR drop and hotspot temperature are proposed to evaluate the characteristics of BSPDN. The impacts of different activity factors, interconnecting metals and structure ratios are investigated. The results indicate that BSPDN faces the severer thermal challenges than FSPDN after the substrate thinning. And the design guidance of BSPDN is given for improving its performance at advanced node.
We propose a new single-electron (SE) reaction-diffusion (RD) circuit that can express traveling plane waves. While SE circuits have advantages such as nonlinearity and stochastic behavior, a suitable information processing method has not yet been established for them. Thus, we focus on the behavior of a photo-responsive (PR) Belousov-Zhabotinsky (BZ) reaction, one of RD systems, to develop a suitable information processing method. Reportedly, the PR-BZ reaction can generate plane waves, and the waves can be used to represent logic gates. Here, we designed the new SE-RD circuit that can generate the desired plane waves. In simulation results, we found our circuit can operate as desired. We believe this circuit can be used to construct a logic gate device as same as the PR-BZ reaction.
Graphene nanoelectromechanical (GNEM) switches have recently gained much attention due to their low leakage current, sharp switching, and high ON/OFF ratio. However, one bottleneck in GNEM switches is the irreversible stiction between graphene and the metal contact. This study walks through the various ways by which we overcame this issue while achieving a low pull-in voltage (< 0.5 V), an increased number of cycles (> 50,000) and sub-thermal switching (≈10mV/dec).
We designed the single-electron (SE) reservoir computing (RC) circuit using multiple-tunnel-junction SE oscillators (MJSEOs), which was compared to a previous SE RC circuit that utilized standard SEOs. The learning performance of the circuits was evaluated by root-mean-square error (RMSE), and it was found that the SE RC circuit with MJSEOs showed superior performance for waveform prediction than the SE RC circuit with SEOs.
This paper proposes machine learning based etching amount prediction from arm scanning movements for single wafer wet etching to optimize etching recipe. Compared with the conventional prediction method of fixed etching rate, the proposed machine learning methods achieve 0.23 lower RMSE in predicting wet etching amount.
The influence of weight transfer error on vector-matrix multiplication (VMM) in the AND array architecture is investigated. In AND array, a constant voltage is applied to the drain, causing the off-currents of unselected cells connected to the same bitline as the selected cell. The VMM error caused by the off-currents is analyzed and evaluated in AND arrays of varying sizes. The results verify that the current sum error increases proportionally to the square of the number of wordlines (N-WL).
Nanoelectronic devices, despite their energy efficiency and unique features, are often hindered by high variability and unpredictability. Bayesian reasoning, a machine learning technique dealing with random variables, can be a remarkable lead to exploiting nanodevices without suffering from these issues. In this paper, we present two realizations of Bayesian computing concepts based on memristors. First, using memristors as random variables allows the accurate recognition of cancerous tissue images. Second, a "Bayesian machine" is presented, which uses near-memory and stochastic computing for low-energy Bayesian inference.
Essential characteristics of synapse arrays in neuromorphic systems include scalability, low-power operation, and precise vector-matrix multiplication (VMM). This paper investigates an asymmetric dual-gate synapse array that offers a power-efficient weight transfer method. By reconfiguring the arrangement of asymmetric gates, a 16 $\mathbf{F}^{2}$ cell-sized synapse array was produced. In addition, the array was fabricated with a buried-bottom gate structure, minimizing cell size and line resistance.
Based on the physics-inspired many-body effects, we propose a promising design for Boltzmann machine-based invertible logic (IL) implemented with probabilistic bits. Simple conventional XNOR gates are selected to implement the many-body interactions. We first present the family design of the many-body-based IL, further proving the composability with large-scale integer factorizers (IFs) consisting of fundamental IL gates. The many-body IL design induces degeneracy in energy landscapes, boosting accuracy efficiency significantly. For a logically synthesized 6-bit $\times$ 6-bit IF, the accuracy is enhanced from 4.430% to 88.85%.
A threshold voltage definition for MOS diodes that uses $2\psi_{B}$ surface-to-substrate band bending as the threshold criterion is widely accepted in spite of some inherent weaknesses. Recently, a new MOS diode threshold voltage definition was proposed based on a standardized log-linear charge vs. voltage relationship to overcome shortcomings of the $2\psi_{B}$ definition. In this presentation, effects of quantum confinement on the new definition are analyzed in detail. It is shown that a constant quantum correction on gate oxide thickness will suffice for the new definition to work properly.
In this letter, we propose and experimentally demonstrate a high-speed true random number generator (TRNG) by exploiting the probabilistic delay time of threshold switching (TS) in a unified selector-resistive random access memory (RRAM). The device consists of dual functional layers (VO2/HfOx) and exhibits high endurance and fast switching speed, enabling a high bit generation rate (>28M/s). The switching parameters have been comprehensively investigated to obtain a stable and fine entropy. The generated bitstream successfully passes 12 National Institute of Standards and Technology (NIST) statistical tests without any postprocessing. The randomness and independence of the entropy source are justified by the autocorrelation test at a 95% confidence level, demonstrating great potential in high-performance hardware security and stochastic computing implementations.
In this paper, we propose a solution that involves adding a silicon nitride (Si3N4) layer to the spherical shallow trench isolation (STI) structure. By optimizing the spherical STI structure and adding the Si3N4 layer. The addition of Si3N4 is shown to cause a decrease in pass gate effect (PGE) based on the measurement results. The proposed structure reduced the PGE compared to the currently used BCAT structure.
An in-depth physics-based investigation of source/drain extension region on Nanosheet FET (NSFET) is presented in this work. A drain-extended NSFET exhibit ∼15× decrement in I OFF with no significant decrement in I ON as drain extension length (L D, EXT ) increases from 1 to 8nm, I OFF can further be lowered (∼6.5×) by symmetric NSFET at the cost of ∼1.5× reduction in ION, which can be handled by stacking. NSFET with LEXT of 4∼,6nm gives optimum performance owing to the trade-off between SS and V T, ON . An asymmetric increment of extension length decreases the capacitance of the same side while increasing the capacitance of the other side. For applications requiring larger intrinsic capacitance, symmetric NSFET would be a good choice which gives higher Cgg (∼,1.5×) than other counterparts with longer extension lengths. DIBL and NM strengthen the optimum selection of LEXT to be between 4∼6nm. Drain-extended NSFET again outperforms in propagation delay and EDP.
We present a new V th -mismatched loadless 4T SRAM TRNG MACRO. The MACRO includes 2 sub-arrays. 1 array comprises $16\times 16$ 4T-SRAM cells. Instead of latch-effect, process-induced V th - mismatch is as entropy of the TRNG in 40-nm CMOS technology. Since 4T-SRAM is volatile, “read-just-after-write” (RAW) scheme is designed to readout random bits immediately after bits are just written, and the DQ-FF parallel-in-and-series-out (PISO) is to register random-bits to output. We execute the RAW scheme in 16 cells in the same row for both arrays simultaneously to generate 32 random bits at once, in terms of 32x bandwidth expansion. Results show that good-quality random-bits can be generated at $\mathrm{V}_{\text{BL}}=0.65\mathrm{V};\ \mathrm{V}_{\text{WL}}=0.85\mathrm{V}$ in 6ns with 400 MHz of clock, in terms of 0% of bit-error-rate; 49.91% of mean with 4.63% of standard deviation for the Hamming-distance; 50% of the Hamming-weight; 0.9997 of entropy. Moreover, energy efficiency is 0.82 pJ/b $n$ ; performance is 3.64 TOP/W.
Germanium selenide (GeSe) is a highly promising material with several attractive characteristics, particularly in the field of ferroelectric and phase-change memories due to its outstanding electronic behavior. However, the potential of GeSe as a charge-trapping layer in flash memory has received less attention. Herein, the fabrication of a nonvolatile MOS memory device using GeSe nanosheets as a charge-trapping layer was demonstrated and the materials flakes were examined extensively. The electrical performance of the memory device was investigated. Intriguingly, it exhibited an extraordinarily wide memory window of 9 V under ±10 V electrical biasing. Additionally, the devices presented high endurance of $10^{4}$ programming and erasing cycles, and reliable charge storage of only 56% loss after 10 years.
A novel Ge condensation process using low temperature supercritical phase fluid (SCF) was proposed on SiGe/Si GAAFET. Device with a Ge condensation by SCF treatment exhibits higher $\mathrm{I}_{\text{ON}}$ , lower $\mathrm{I}_{\text{OFF}}$ , larger $\mathrm{I}_{\text{ON}}/\mathrm{I}_{\text{OFF}}$ , lower S.S., higher uniformity and better reliability, due to the enhanced mobility by the reduction of vacancy defects in $\text{SiGe}$ and interface traps or/and reversed tensile strain in Si.
