In this paper, the interest of low-k, low temperature SiCO deposition at 400°C as offset spacers is highlighted through FDSOI MOSFETs low temperature process integration. The excellent material and electrical properties as compared to SiN 630°C POR reference, ensures the integrability of SiCO for 3D VLSI integration and its interest for advanced nodes.

Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

We present recent progress on vertically stacked-wires MOSFETs with a replacement metal gate process for CMOS scaling beyond FinFET technology. Key technological challenges (such as 3D integration process including inner spacer, mobility, and strain engineering) will be discussed in relation to recent research results.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (<;100nm) offers new 3D partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress and High Performance (HP) digital stacked FETs for computing application can be achieved with a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB can be used between stacked tiers. Ultra-Low TB FETs (<;400°C) have potential for low-power applications and allow for the stacking of multiple layers.

Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 10 8 /mm 2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances as high temperature ones while fulfilling the PBTI and hot-carrier effects reliability requirements, comforting the viability of N over CMOS approach.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

2016 International Conference on Solid State Devices and Materials,Influence of Low Thermal Budget Plasma Oxidation and Millisecond Laser Anneal on Gate Stack Reliability in view of 3D Sequential Integration

We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF 2 ). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

Raising the sources and drains regions of Fully Depleted Silicon-On-Insulator devices is mandatory in order to have enough material for silicidation and obtain low contact resistances. Doping was until the 28 nm technology node carried out using ion implantation. For a variety of reasons, in-situ doping is mandatory in future node transistors, however. We have thus focused on the in-situ phosphorous doping of the Si Raised Sources and Drains (RSDs) used in n-type devices. We have shown in [1] that reduced pressures (e.g. 20 Torr) were harmful in order to obtain at 750°C-800°C high P+ ions concentrations with reasonable Si:P Growth Rates (GR). With SiH2Cl2 + PH3 + HCl, we indeed saturated at [P+] around 1019 cm-3, with a surface poisoning by P atoms that drastically decreased the Si:P GR. Wanting to have a straightforward Si:P co-flow process instead of a more complex Cyclic Deposition/Etch process [2], we have thus studied the in-situ phosphorous doping of Si and Si1-yCy at Atmospheric Pressure (ATM) and in the 700°C – 800°C range. To that end, we have proceeded as follows. In order to gain access to the Si1-yCy:P layer thickness and confirm that layers were indeed single crystalline, we have grown {Si0.8Ge0.2 / Si1-yCy:P} stacks on Si(001) and measured them with X-Ray Reflectivity (which gives access to thickness) and X-Ray Diffraction (crystalline quality assessment), as shown in Figure 1. We have otherwise grown the very same Si1-yCy:P layers on slightly p-type substrates to have pn junctions and determine through four point probe measurements their sheet resistances. Resistivities and thus P+ ions concentrations were extracted by multiplying those by the Si1-yCy:P layer thicknesses (from XRR). We have plotted in Figure 2 the Si:P growth rate and [P+] at 750°C, ATM, this for increasing F(PH3)/F(SiH2Cl2) Mass-Flow Ratios (MFRs). When the SiH2Cl2 mass-flow was fixed, we had a significant increase of the Si:P GR (up to 13.3 nm/min.) and of [P+] (at most 7x1019 cm-3). We have tried to reach higher MFRs by reducing, for the highest PH3 1% in H2 flow deliverable in our tool, the SiH2Cl2 mass-flow. This led to (i) a Si:P growth rate decrease and (ii) to a slight [P+] decrease, instead of the increase hoped for. We have studied in Figure 3 the impact of growth temperature on the Si:P GR and on [P+] for the optimum point of Fig. 2. The activation energy associated with the Si:P growth rate increase with temperature in the 700°C-800°C range was equal to 53 kcal. mol.-1 (e.g. close to the Si-H bond strength), while [P+] was steady at 7x1019 cm-3. We have thus moved over to a PH3 5% in H2 bottle and quantified, at 700°C, ATM, the impact of the PH3 flow on the Si:P growth rate and n-type doping for fixed SiH2Cl2 and HCl mass-flows. We have in Figure 4 a sharp increase, a stabilization then a Si:P GR decrease as the PH3 flow increases, which might be due to surface poisoning. Such a behaviour is associated with a P+ ion concentration that sharply increases then reaches a plateau close to 1020 cm-3. We have used such a co-flow processes to thicken at 725°C, ATM the sources and drains regions of stacked Si nanowires with 50 nm of Si:P. The surface of those RSDs was slightly rough (as for Si:P layers on blanket substrates). Full selectivity versus SiO2 (Buried OXyde) and SiN internal spacers was achieved, however, as illustrated by the SEM images of Figure 5. Finally, we have studied the feasibility of adding SiCH6 to the gaseous mixture in order to have C atoms that would supress B diffusion (p+ pockets to control short channel effects in bulk nMOS transistors) and hopefully inject tensile strain in short Si channels (if the substitutional C content is high enough). Because of the rather high temperature (700°C), we were not able to obtain [Csubst.] above 0.55%, as shown by Figure 6 XRD profiles. We were otherwise faced with a Si1-yCy:P GR that decreased and a layer resistivity that increased as the SiCH6 mass-flow increased (competition between P and C atoms for incorporation in the lattice and electron mobility degradation because of the small size of the C atoms), as shown in Figure 7. The best trade-off was achieved for a F(SiCH6)/F(PH3) MFR close to unity. [1] J.M. Hartmann et al, J. Cryst. Growth 264 (2004) 36 and J. Cryst. Growth 310 (2008) 62. [2] J.M. Hartmann et al., Semicond. Sci. Technol. 28 (2013) 025017 and 025018. Figure 1

Low temperature epitaxy is today necessary in thin film Fully Depleted SOI (FDSOI) MOSFETs in order to obtain good quality accesses. Indeed, high temperature process has been shown to be detrimental for the growth of raised sources and drains (RSD) on thin films, as dewetting of the starting film and/or islanding of the epitaxial layer can occur [1]. Besides, low temperature epitaxy is also a key enabler for 3D sequential CoolCubeTM integration, where the 3D fabrication of devices one on top of the other and on the same substrate requires low thermal budget processes (typically T<500°C) in order to avoid the degradation of the bottom layer [2]. However, development of low temperature epitaxy faces several challenges: contaminated starting surface, growth rate exponential decrease, lesser epitaxial layer quality or loss of selectivity over dielectrics to give few examples. In this work, through morphological observations and analysis of electrical devices, we will describe different approaches we use to solve these problems. Surface preparation is one of the most critical steps as it directly influences the subsequent epitaxy. Presence of contaminants (C, O, F mostly) can lead to lower growth rates and/or morphological defects in the epitaxial layer. High temperature H2 pre-bake (T>1000°C) yields H-passivated and contaminants-free surfaces, yet it is not compatible with thin films technologies. Nevertheless, native oxide can be removed using a “HF-last” wet clean as well, allowing a reduction in the pre-bake temperature necessary for a good surface preparation (750°C-775°C in [3]). Besides, native oxide can also be removed using the Siconi process, where a NH3/NF3 dry plasma transforms the oxide into a salt which can then be sublimated at temperatures below 200°C [4]. In our work, we show the influence of wet and dry cleans on the quality of the subsequent raised sources and drains epitaxy, the best surface being obtained when using both processes successively (Figures 1a to 1c). Using the optimum wet and dry cleans combination, the thermal budget of the H2 bake could then be reduced from two steps (650°C 2min + 750°C 30s) down to 650°C 2min only. Although higher concentration of interfacial contaminants is to be expected with a lower thermal budget H2 bake, we found no morphological degradation after our standard 650°C epitaxy of SiGe:B raised sources and drains. (Figure 1d). Additionally, equivalent electrical performances were obtained with the lower thermal budget bake (Figure 2). In a second time, the epitaxy temperature was also decreased. High order silanes (e.g. Si3H8, Si5H12) have been proposed to cope with the drastic Si growth rate decrease at low temperatures [5-6]. However, these liquid precursors are very costly, making them less appealing for industrial use. Meanwhile, use of germane (GeH4) and diborane (B2H6) also yields higher growth rates thanks to the preferential desorption of H atoms on B and Ge surface sites. Hence, SiGe:B epitaxy at 500°C was evaluated structurally in a previous work [7]. At such a low temperature, straightforward co-flow selective epitaxial growth (SEG) using chlorinated gases (SiH2Cl2 or HCl) is not possible anymore. Selectivity is then achieved using a deposition/etch (D/E) approach using Si2H6, GeH4 and B2H6 as growth precursors and HCl for the selective etching of polycrystalline materials on dielectrics. Good quality 2D epitaxial layers can thus be obtained with full selectivity over the buried oxide and the nitride gate spacer (Figure 1e). We also show that doubling the number of cycles (i.e. to D/E/D/E strategy) yields smoother access regions, yet at the cost of the selectivity (Figure 1f). Use of more reactive chlorine gas is therefore proposed to obtain desired selectivity at 500°C. Finally, for the first time, pMOSFETs on thin SOI (tSi=11nm) substrate were fabricated using the new 500°C D/E recipe for SiGe:B raised sources and drains and functional transistors were obtained (Figure 3). A thorough electrical analysis of these devices (e.g. access resistance, mobility) will be provided in this work. [1] Y. Ishikawa et al., Appl. Surf. Sci. 90, 11-15, 2002. [2] P. Batude et al., Proceedings of 2015 VLSI Technology Symposium, 48-49, 2015. [3] A. Abbadie et al., Appl. Surf. Sci. 225, 256-266, 2004. [4] M. Labrot et al., Appl. Surf. Sci. 371, 436-446, 2016. [5] A. Gouyé et al., Appl. Phys. Lett. 96, 063102, 2010. [6] J. C. Sturm et al., ECS Trans. 16 (10), 799-805, 2008. [7] J-M. Hartmann et al., ECS J. Sol. State Sci. Technol. 3, 382-390, 2014. Figure 1

Stacked-NW FETs pave the way for significant increase in device effective width over FinFET and FDSOI. An increase of performance and/or a decrease of device footprint is expected by using thin and wide NW channels also known as nanosheets or nanoplates. This paper points out Gate Last integration issues of stacked-NWs. Two solutions labeled as NW First and NW Last are presented featuring internal spacer formation. A demonstration of self-aligned gate and spacers is proposed, involving Hydrogen Silsesquioxane (HSQ) lithography through silicon channels.

Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.