The Boolean satisfiability (SAT) problem is a fundamental NP-complete problem, and efficiently solving it would revolutionize fields like optimization, artificial intelligence, cryptography, software, and hardware verification. Physics-inspired computers offer significant advantages, including continuous-time (CT) operation, massive parallelism, and increased energy efficiency. Solvers that map the optimization objective to a dynamical system of spins [1] have been shown to outperform classical discrete optimization solvers. Recent work maps 3-SAT to systems of coupled spins but suffers from long solution times or low solvability [2], [3], and is limited to problems with only 20 variables [3]. [4] decomposes 3-SAT problems to an all-to-all connected analog lsing machine, but the proposed iterative compute scheme results in ms-level solution times. A digital solver based on an array of processing elements (PEs) [5] has reported competitive performance, but it does not account for the substantial preprocessing time and energy required to embed the problem into the available hardware - embedding itself is a complex optimization problem. Furthermore, the system in [5] can connect only up to 32 clauses to a given variable, limiting its ability to solve real-world satisfiability problems where some spins are highly connected.

Analog compute in memory (CIM) with multilevel cell (MLC) resistive random access memory (ReRAM) promises highly dense and efficient compute support for machine learning and scientific computing. This article introduces analog to digital converter (ADC)-assisted bit-serial processing for efficient, high-throughput compute. Bit-serial digital to analog converters (DACs) and 8-bit binary-weighted multicycle sampling (BWMCS) ADCs perform analog vector-matrix multiplication (VMM) on MLC-based crossbar arrays. A direct drive gm-boosted transimpedance amplifier (TIA) enables high-speed crossbar readout. We present a system on chip (SoC) prototype consisting of four self-contained ReRAM-based CIM macros and a reduced instruction set computer-five (RISC-V) host. The test chip is fabricated in 65 nm CMOS with foundry-integrated MLC ReRAM. We trained LeNet1 for handwritten digit classification and mapped the CNN weights differentially to 3-bit MLC ReRAM across multiple CIM macros. The classification accuracy loss is 1.6% when compared to the quantization-aware trained model. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.

Drawing insights from quantum computing, oscillator-based computing leverages continuous-time operation and massive parallelism to accelerate challenging computational tasks. This work advances the field to demonstrate a Combinatorial Optimization Problem (COP) engine for efficient, robust, one-shot oscillator-based soft decoding of LDPC codes for the first time. We present a 28nm CMOS prototype that achieves a Frame, Bit Error Rate (FER, BER) of 1.38 x 10(-5), 1.25 x 10(-6) respectively at 7dB SNR and an energy efficiency of 5.26 pJ/bit, which surpasses the normalized efficiencies of recent state-of-the-art decoders [1][2][3] by 11x, 3x, 1.5x respectively. Tested with more than 100 million frame decodings, the prototype demonstrates consistent performance across a range of SNRs, supply voltages, and temperatures.

Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm 2 .