Analog compute in memory (CIM) with multilevel cell (MLC) resistive random access memory (ReRAM) promises highly dense and efficient compute support for machine learning and scientific computing. This article introduces analog to digital converter (ADC)-assisted bit-serial processing for efficient, high-throughput compute. Bit-serial digital to analog converters (DACs) and 8-bit binary-weighted multicycle sampling (BWMCS) ADCs perform analog vector-matrix multiplication (VMM) on MLC-based crossbar arrays. A direct drive gm-boosted transimpedance amplifier (TIA) enables high-speed crossbar readout. We present a system on chip (SoC) prototype consisting of four self-contained ReRAM-based CIM macros and a reduced instruction set computer-five (RISC-V) host. The test chip is fabricated in 65 nm CMOS with foundry-integrated MLC ReRAM. We trained LeNet1 for handwritten digit classification and mapped the CNN weights differentially to 3-bit MLC ReRAM across multiple CIM macros. The classification accuracy loss is 1.6% when compared to the quantization-aware trained model. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm2.

We report on a reduced thermal budget for hybrid bonding anneal using a single wafer thermal processing system (TPS). Robust bonding with excellent Cu gap closure and grain growth across the interface was achieved using a single step 300°C 5min TPS anneal, thereby reducing anneal duration by two orders of magnitude compared to the industry standard furnace anneal. The Cu gap closure efficacy with 350°C 5min TPS anneal was further verified electrically through functional 2Mb viachains @ 0.5um pitch with a Rs/link <5 Ohm.

New mobility improvement solutions are proposed for next generation SiC trench MOSFET with higher aspect ratio trenches. A combination of channel counter-implant and pocket implant is shown to be most effective for improving mobility without V T loss. Using our proposed integration scheme and calibrated modeling, we project an 80% improvement in mobility and 40% improvement in channel resistance, realizing the true potential of trench MOSFET architecture for next generation SiC power device technology.

New material, process and device design innovations are proposed for next generation SiC trench MOSFET. Advanced patterning films (APF) are proposed as novel implant hardmask and high temperature capping material. Novel gate oxide formation processes are demonstrated for improved pattern fidelity & carrier mobility. A novel SiC transistor device design integrating channel counter-implant and pocket implant is proposed for significant mobility improvement without threshold voltage $(\mathrm{V}_{\mathrm{T}})$ loss.

In this paper, we present a modeling framework to simulate the electrical characteristics of SiC MOSFET. Our model also describes the mobility improvement with counter doping in channel. Our analyses show improved drive current and degraded/lower threshold voltage with a counter-doped channel. To this end, we investigate the impact of varying the doping concentrations of the counter-doped region and the underlying p-well for optimum device performance.

The constant drive to achieve higher performance in deep neural networks (DNNs) has led to the proliferation of very large models. Model training, however, requires intensive computation time and energy. Memristor-based compute-in-memory (CIM) modules can perform vector-matrix multiplication (VMM) in place and in parallel, and have shown great promises in DNN inference applications. However, CIM-based model training faces challenges due to non-linear weight updates, device variations, and low-precision. In this work, a mixed-precision training scheme is experimentally implemented to mitigate these effects using a bulk-switching memristor-based CIM module. Low-precision CIM modules are used to accelerate the expensive VMM operations, with high-precision weight updates accumulated in digital units. Memristor devices are only changed when the accumulated weight update value exceeds a pre-defined threshold. The proposed scheme is implemented with a system-onchip of fully integrated analog CIM modules and digital sub-systems, showing fast convergence of LeNet training to 97.73%. The efficacy of training larger models is evaluated using realistic hardware parameters and verifies that CIM modules can enable efficient mix-precision DNN training with accuracy comparable to full-precision software-trained models. Additionally, models trained on chip are inherently robust to hardware variations, allowing direct mapping to CIM inference chips without additional re-training.

Despite the great promises of resistive random-access memory (ReRAM) for fast, low-power in memory computing, the models deployed on ReRAM crossbars suffer from accuracy loss, due to poor yield, inaccurate switching and high noise. In this paper, we report a forming-free bulk ReRAM (b-ReRAM) cell that can be programmed up to 128 levels between 400nA $(4\mu \mathrm{S})$ and $4\mu A (40\mu S)$. The device operates by continuous modulation of bulk oxygen vacancies, therefore exhibiting favorable characteristics including forming-free operation, analog switching, low noise and low operating currents [1], [2]. The multilayer ReRAM stack is deposited using a specially built 300mm deposition system that features a clustered sequence of Physical Vapor Deposition (PVD) and Atomic Layer Deposition (ALD), leading to high wafer-level yield and uniformity. High programming accuracy can be achieved over 25k b-ReRAM devices across 15 dies. A fully integrated system on chip (SoC) with BEOL-integrated b-ReRAM arrays is built with 65nm CMOS technology, and keyword spotting (KWS) is demonstrated with accuracy equivalent to the software quantized model and high energy efficiency at 98.5 TOPS/W. Moreover, we evaluate the performance of the bitcell for large neural network (NN) applications in a custom hardware-aware simulation platform and show that software comparable accuracy can be achieved. This work for the first-time reports that high yield and high programming accuracy can be achieved with b-ReRAM at the wafer-level scale and demonstrates that superior analog behavior enables the mapping of NN models onto the ReRAM-based SoC prototype with no accuracy loss and high energy efficiency.

Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm 2 .

This letter reports a new method using boron plasma doping and nanosecond laser annealing for further improvement of contact engineering. Up to 8% device performance improvement is demonstrated by using this technique in a conventional FinFET architecture. The key value of this letter relies on the plasma doping of fin vertical sidewalls and the super-activation of dopants, without any volume consumption between the epitaxial source and the drain. Furthermore, the TCAD simulation result points out that combining this method with the wrap-around contact structure can double the boost of transistor performance. We believe that this will bring us a new milestone in ultra-low contact resistance.

This paper addresses novel approaches at material and integration fronts for gate applications. Material wise, new n work function metal (WFM) material is explored to address the need for reducing gate resistance and maintaining proper Vt at 20A or less WFM thickness. Integration wise, next generation dipole is tested with various process sequences to address the need in lowering overall thermal budget at the gate level for advanced architectures, such as scaled FinFET and Nanosheets.

In this paper, we demonstrate a novel Source Drain Extension (SDE) approach to enable NMOS device scaling along with improved performance. For the first time, SDE formation with epitaxially grown As doped Si (Si:As) has been examined and compared to the current state-of-the-art SDE formation in FinFET at 10nm logic ground rules. It is found that a Si:As layer based SDE provides a clear improvement in the short channel effect and a significant device performance increase. It is also shown that a careful co-optimization of the Si:As layer and Source / Drain (S/D) lateral recess is required to achieve the optimum device gain. This paves the way for the ultimate nSDE formation for current and next generation CMOS devices.

This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell sizing options, including a 1-fin-per-device version and a 2-fin-per-device design, are systematically evaluated. Each device flavor has multiple vertical stacks when wire-like or slab-like structure is used. Comprehensive transistor and logic cell studies demonstrate that the novel NR is the optimal structure for N5 and beyond.

We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B contact resistivity (rho(c)) down to 2.1x10(-9) Omega.cm(2) (a 40% reduction vs. PVD Ti), matching the lowest published values [1-5]. A competitive n-type CVD Ti/Si:P with a rho(c) at 2.6x10(-9) Omega.cm(2) is measured. We demonstrate up to 90% superconformality for this process, with a tunnel silicidation at lengths up to 500nm, showing an exceptional selectivity to oxide. This process is an enabler for the next generation of area-enhanced contact CMOS architectures.

Inline detection of embedded voids within Middle-Of-Line (MOL) cobalt metal lines is a major industry gap at 7nm technology node and below, for both developing the new metallization solutions, as well as for monitoring during ramp and production. We present a new non-destructive electron beam cobalt void detection method, leveraging an improved scanning electron microscope (SEM) imaging technique, which enable an accurate detection of voids embedded inside MOL metal trenches. After explaining the potential process mechanisms causing void formation, we introduce the e-beam technique, and demonstrate by simulation and experiments the correlation between the electron signal and the volume and depth of the voids. We conclude this paper by discussing how a defect inspection strategy using a massive metrology approach can lead to a faster and more efficient development of the Cobalt metallization.

We report a record-setting low NMOS contact resistivity of 1.2×10 −9 Ωcm 2 compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ C to below 1×10 −9 Ωcm 2 for the post 7 nm nodes.

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

In the past decade, the surge of demand for mobile devices has been tremendous, and has been a key growth engine for the semiconductor market. These novel devices have all capabilities for sophisticated mobile communication, as well as capabilities for gaming, computing, etc. To address the stringent requirements in terms of battery lifetime, device speed, and scaling, the design and manufacturing processes of mobile devices needs constant innovation. Historically, Group IV epitaxial processes such as e-SiGe source/drain have played a critical role in meeting the needs for device scaling and performance in planar devices. One dramatic change that has taken place to address device scalability is the move to the multigate architecture of the FinFET (Fin Field Effect Transistor), which enables the virtual increase of the gate length and dramatically improved electrostatic performance. Beyond FinFET, the GAA (Gate All around Transistors) device structure is one of the most promising paths for offering another disruptive leap in device scaling. This paper discusses the increasingly critical role of epitaxy applications for enabling both of these new device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices. We first review the overall trends for advanced CMOS devices in terms of scalability and performance. To carry on Moore’s law, devices need to be scaled from node to node. To enable this scaling, taller, more rectangular FinFETs with narrower body width at scaled pitches has been demonstrated. However this leads to several key process and integration challenges such as Fin integrity, capacitance increase, Channel mobility, sub-fin isolation, sidewall doping as well as contact resistance reduction. Next, we review the challenges of increasing FinFET device performance (e.g., mobility boost) by using SiGe p-channel FinFET, which has gained quite a lot of attention in the past several years. Several SiGe integration approaches have been reported in the literature, all which are enabled by new epitaxy applications. Examples of these SiGe channel integration approaches include SiGe replacement channel, STI last SiGe formation, cladded SiGe and SiGe condensation. There are significant integration challenges for each of these approaches from the perspective of epitaxial growth and related processes. For example, each of SiGe channel formation schemes have some specific requirements not only on the pre-clean and/or epi growth but also on the overall CMOS integration scheme (alleviation of SiGe oxidation, recess, Fin shaping, junction formation etc.). Consideration of the entire process flow is critical to ensure maximum strain is achieved in the channel with very low defectivity – two critical requirements for High Volume Manufacturing of high performance, low power devices. These topics will be explored in detail for several of the integration approaches mentioned above. Finally, we will discuss the potentially disruptive transition to a new device architecture – the Gate-All-Around (GAA) transistor - and discuss new epitaxy opportunities, requirements and challenges for this new device type.

We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the source/drain, self-aligned on the contact trench. A record low p-type contact resistivity of 5.9×10 −9 ohm-cm 2 is demonstrated and a 7.5% performance improvement is achieved. The variation of the implant temperature demonstrates a further improvement of the contact resistance when going to cryogenic (cold) implantation (−100 °C). Using TCAD, we demonstrate that the reduced implant temperature provides a higher degree of amorphization and reduces defects. This is the key to provide an enhanced recrystallization of the doped amorphized region through Solid Phase Epitaxial Regrowth (SPER) low temperature activation. We propose in this paper a novel mechanism for p-type contacts, and demonstrate it for the first time on state-of-the-art FinFET p-type devices using cryogenic (cold) implants and SPER regrowth.

We demonstrate a thermally stable titanium silicide/titanium nitride (TiSix/TiN) full metal gate (FMG) for dual-channel gate-first high-k/metal gate complementary metal-oxide-semiconductor technology. Unlike prior tungsten-based FMG, the simple TiSix/TiN gate electrode does not require any additional barrier layer preventing oxygen down-diffusion during high-temperature processing, as the TiSix itself blocks oxygen. With HfO2-based gate dielectrics and without any oxygen scavenging scheme, we thus demonstrate a capacitance-equivalent thickness in inversion (T-inv) of 1.11 nm, corresponding to an equivalent oxide thickness of similar to 0.7 nm. Silicon channel nFET and silicon germanium channel pFET parametrics are similar to those of control devices utilizing a conventional a-Si/TiN metal-inserted poly-Si stack (MIPS) gate, while providing superior gate sheet resistance. By supplanting MIPS with such an FMG, we anticipate that contacted gate pitch can be scaled aggressively via reduced gate height and borderless source/drain contacts.