FSMLock is a memory-based finite state machine locking methodology that uses memory and private key cryptography to protect FSM-based IP. It was designed to counteract several threats found within the IC design industry, and was assembled into its own toolset to be customizable according to provided parameters of a protected FSM. Though FSMLock has seen significant changes and improvements, including the addition of Finite State Machine Input Multiplexing (FSMIM), there are still some considerations related to its cost (size), performance, and usability. This paper provides detailed analysis of the theory behind memory-based FSM implementations, like FSMLock, to determine all important considerations & constraints for input FSM features based on a given memory size. Given that memory usage is a critical constraint on the usability of FSMLock, designing FSMs for optimized memory usage and utilization is key.

FSMLock is a sequential logic locking technique that has been proposed for protection of intellectual property (IP) of finite state machine (FSM) circuits. While this technique provides security advantages over other sequential logic locking techniques, one major drawback this approach brings is the large amount of memory required for storing data of all states, transitions, and outputs. Finite State Machines with Input Multiplexing (FSMIM) is an optimization methodology and tool that was proposed for efficient mapping of FSMs into memory. This is primarily achieved by reducing the number of effective inputs to the FSM. This paper discusses our work on integrating these two techniques in a practical case study of converting existing state machine into implementation with FSMLock with input multiplexing.

FSMLock is a new sequential logic locking technique that utilizes classical cryptographic block cipher algorithms to conceal and restrict access to the targeted finite state machine (FSM). Unlike other FSM-based sequential logic locking techniques, FSMLock adds no additional states to the state transition graph (STG). Instead, FSMLock is applied to a sequential circuit by abstracting a flattened version of its distinct state entry table (SET) into a binary data file, which can then be encrypted and stored in non-volatile memory (NVM). The encrypted flattened stats entry table (FSET) information is read in partitions such that, at run-time, only a subset of the sequential logic is in scope. The resulting architecture has a theoretical resistance against removal attacks, circuit unrolling-based satisfiability (SAT) attacks, and topological/boolean functional analysis attacks. This is due to the SAT-hard abstraction as an encrypted binary data file of the locked circuitry.

Protecting system's memory was researched in the past, and there are several methods of achieving it such as memory encryption, memory hashes, and message authentication codes. To overcome associated performance overhead, authentication tree designs have been proposed, for example, well known Merkle tree, TEC-tree or dynamic authentication tree (DAT). This work builds on the top of the DAT design by integrating tree node caches and evaluating the improved viability of the approach. Our cached design was implemented on a Xilinx Zynq-7020 APSoC with a hard core CPU communicating with the fabric-based memory protection controller. The addition of caches to the dynamic authentication tree design increased the performance enough to be competitive with TEC-Tree, and in scenarios that frequently access previously processed data, the cache-added DAT was able to outperform TEC-Tree based designs.

MK-3 is an authenticated encryption scheme based on the duplex sponge construction, suitable for both hardware and software. It provides broad factory and field customization features. The same security claims are valid for the original and all recommended customizations. Extensive security analyses of MK-3 were performed in our previous work: differential, linear, cube, and brute force attacks, as well as statistical analysis. In this work we report on new experiments involving Correlation Power Analysis (CPA), which is considered one of the most powerful side-channel attack (SCA) techniques. Two CPA attacks on MK-3 were developed: the first directly after the key absorption, and the second after the S-boxes in the first round of IV absorption. In the first attack, under strong assumptions about an attacker's capability to collect traces, we can recover 128 of the 512 state bits in a physical test on an FPGA. The second attack builds on top of the first one, but it assumes that special registers have been embedded after the S-boxes. Even under such ideal conditions, this attack can potentially reduce the brute-forcing difficulty only by an additional 88 to 194 bits. Overall, this gives the CPA attack no advantage over brute-forcing for the original 128-bit key. The previous and current results ensure that MK-3 and its customized versions effectively conceal its plaintext input.

To provide security autonomy capability, such that different users can have independent variants of the encryption algorithm, MK-3 is designed to be customizable. Two levels of customization are supported, Factory Customization and Field Customization. Customization is done by modifying functions and function parameters in the algorithm to yield differing cipher functions while preserving the algorithm's security. The main goal of this work is to present the results from the statistical analysis of the customizable MK-3 encryption scheme, focusing on field customized mixers. We recall the main components of the MK-3 algorithm and overview a subset of available factory and field customizations for MK-3. We test the main instances of the field customized versions and give a general argument for their desired statistical properties expected from an encryption scheme.

As embedded devices increase in use and handle more critical information and functionalities, the importance of security grows even greater. Defense against bus attacks such as spoofing, splicing, and replay attacks is of particular concern. Traditional memory authentication techniques, such as hashes and message authentication codes, require significant amounts of on-chip memory and introduce a large performance impact when protecting off-chip memory during run-time. Balanced authentication trees such as the well-known Merkle tree or TEC-Tree can be used to reduce this cost. This work proposes a new method of dynamic authentication trees, which updates a tree structure based on a processor's memory access pattern. An HDL model for use in an FPGA has been developed as a transparent and highly customizable AXI-4 memory controller. The performance of our tree design is comparable to that of the TEC- Tree in several memory access patterns. Speedup over the TEC- Tree is possible to achieve when applied in scenarios that frequently access previously processed data.

A Cross Domain Problem (CDP) is the question of how to securely access and exchange information between the domains of varying security levels. A Cross Domain Solution (CDS) addresses the CDP by designing the framework and protocols for such access and transfers. Most existing CDS methods rely on policies and trusted parties to manage different security levels. A CDS that can function in the presence of untrusted parties is a challenge. Functional Encryption (FE) is an encryption scheme in which a secret key allows one to compute a specific function of plaintext from the ciphertext. FE is a generalization of identity-based and attribute-based encryption frameworks. General and simultaneously practical FE is an emerging area, and only special types of encryption schemes and functions are effectively handled within existing systems. We apply the concepts of FE to explore a new solution to the CDP, and we argue that our solution does not leak information, provided that widely accepted assumptions about standard digital signatures hold. We built a practical software case study application using a trusted Key Distribution Center (KDC), a standard symmetric key block cipher component (like the AES), and using the Elliptic Curve Digital Signature Algorithm (ECDSA). The experiments show that the computational overhead introduced to routing by our method is cost effective, where the additional cost is equivalent to just a few applications of standard digital signatures.

At different stages of the Integrated Circuit (IC) lifecycle there are attacks which threaten to compromise the integrity of the design through piracy, reverse engineering, hardware Trojan insertion, side channel analysis, and other physical attacks. Some of the most notable challenges in this field deal specifically with Intellectual Property (IP) theft and reverse engineering attacks. One method by which some of these concerns can be addressed is by introducing hardware obfuscation to the design in various forms. In this work we evaluate the effectiveness of a few different forms of netlist-level hardware obfuscation of a 16-bit substitution box component of a customizable cipher MK-3. These obfuscation methods were attacked using a satisfiability (SAT) attack, which is able to iteratively rule out classes of keys at once. This has been shown to be very effective against many forms of hardware obfuscation. A method to successfully defend against this attack is described in this paper. This method introduces a modified SIMON block cipher as a One-way Random Function (ORF) that is used to generate an obfuscation key. The S-box obfuscated using this 32-bit key and a round-reduced implementation of the SIMON cipher is shown to be secure against a SAT attack for at least 5 days.

Recursion is a very efficient abstraction that can be found in definitions of many algorithms. However, recursion can be difficult to implement in hardware and as a result is not supported by the majority of high-level synthesis tools (HLS). This work introduces a new framework for implementing recursive functions in hardware, which we call TreeRecur. TreeRecur uses trees to represent the branching recursive function calls of divide-and-conquer algorithms, which makes it possible to take advantage of their procedure-level parallelism. To allow for design flexibility, TreeRecur executes algorithms using a configurable number of independent function processors. These processors are generated using HLS design flow, making it easy to implement a variety of different algorithms. Functionality of our framework was tested on a field programmable gate array (FPGA) using two simple algorithms and compared against software implementations of the same algorithms. Performance results were collected in terms of execution speed and energy consumption. The execution speeds of TreeRecur are shown to be comparable to software programs when differences in clock speed are accounted for and its energy consumption is up to 11 times better than the software solution's.

High-Level Synthesis (HLS) is the process of generating digital circuits from high-level algorithmic descriptions. One of the major steps in this design approach is scheduling, which uses the Control/Data Flow Graph (CDFG) of the software code and determines in which order operations must occur. Traditionally, the scheduling process is time and memory intensive. In this paper, we present a new approach to replace the conventional scheduling portion of the HLS tool chain. This new technique significantly reduces the complexity of scheduling, resulting in improved memory usage and lower computational effort. The results demonstrate that an average 16 times speedup on the time required to determine the schedule can be achieved, with just a fraction (1/5 on average) of the memory usage, and with only 0 to 6% of added cost on the final hardware execution time.

Custom accelerators for high-precision integer arithmetic are increasingly used in compute-intensive applications, in particular homomorphic encryption schemes. This work seeks to advance a strategy for faster deployment of these accelerators using the process of high-level synthesis (HLS). Insights from existing number theory software libraries and custom hardware accelerators are used to develop a scalable implementation of Karatsuba modular polynomial multiplication. The accelerator generated from this implementation by the high-level synthesis tool Vivado HLS achieves significant speedup over the implementations available in the highly-optimized FLINT software library. This is an important first step towards a larger goal of enabling HLS-based homomorphic encryption in the cloud.

A Cross Domain Solution (CDS) is a means of secure information exchange that provides the ability to access or transfer digital data between varying security domains. Most existing CDS methods focus on risk management policies that rely on using protected or trusted parties to process the information in order to solve this problem. A CDS that is able to function in the presence of untrusted parties is a challenge. We apply the concepts of homomorphic encryption (HE) to explore a new solution to the CDS problem. We built a practical software case study application using the Yet Another Somewhat Homomorphic Encryption Scheme (YASHE) around the specific challenge of evaluating the gateway bypass condition on encrypted data. We assess the feasibility of such an application through performance and memory profiling in order to find a parameter selection that ensures proper homomorphic evaluation. The correctness of the application was assured for 64-, 72-, 96-, and 128-bit security parameter selections of YASHE resulting in high latency performance. The computing time required by our proof-of-concept implementation may be high but this approach allows the manual process employed in current systems to be eliminated.

Homomorphic Encryption (HE) allows for encrypted data to be sent to, stored, and operated on by untrusted parties without the risk of privacy compromise. The benefits and applications of HE are far reaching, especially in regard to cloud computing. However, current HE solutions require a large number of resource intensive arithmetic operations such as high precision, high degree polynomial multiplication. This work aims to accelerate the multi-precision arithmetic operations used in HE with specific focus on an implementation of the Schönhage-Strassen Fast Fourier Transform (FFT)-based multiplication algorithm. It is planned to be incorporated into a larger HE library of arithmetic functions tuned for High-Level Synthesis (HLS) that enables flexible solutions for hardware/software systems on reconfigurable cloud resources. The developed FFT based polynomial multiplier exhibits flexibility in the selection of HE security parameters facilitating its use in a wide range of schemes and applications. The design yields substantial speedup over the polynomial multiplication functions implemented in the Number Theory Library (NTL) utilized by software based HE solutions.

MK-3 is a new proprietary authenticated encryption algorithm based on the duplex sponge construction. To provide security autonomy capability, such that different users can have sovereign variants of the encryption algorithm, MK-3 is designed to be customizable. Two levels of customization are supported, Factory Customization and Field Customization. Customization is done by modifying functions and function parameters in the algorithm to yield differing cipher functions while preserving the algorithm's security. This paper describes the MK-3 algorithm's customization options and discusses results of testing designed to verify security autonomy among the customized variants.

Because of the recent break of the SHA-l hash function, it is expected that in the nearest future there will be an increasing interest in the new SHA-3 algorithm. SHA-3 implements a subset of the Keccak family and has been released as the NIST standard in 2015. SHA-3 based MAC is a keyed-hash message authentication function, which can be used to verify both the data integrity of the message and its source. Previous work demonstrated successful side channel attacks, in particular power attacks on hardware implementations of the SHA-3 based MAC. This work presents a new two step practical attack against SHA-3 based MAC implemented on an FPGA hardware. This new attack can successfully extract the 320-bit secret key with 200,000 traces at 90% success rate.

Authenticated encryption (AE) schemes are symmetric key cryptographic methods that support confidentiality, integrity and source authentication. There are many AE algorithms in existence today, in part thanks to the CAESAR competition for authenticated encryption, which is in its final stage. In our previous work we introduced a novel AE algorithm MK-3 (not part of the CAESAR competition), which is based on the duplex sponge construction and it is using novel large 16×16 AES-like S-boxes. Unlike most AE schemes, MK-3 scheme provides additional customization features for users who desire unique solutions. This makes it well suited for government and military applications. In this paper, we develop a new array-based statistical analysis approach to evaluate randomness of cryptographic primitives and show its effectiveness in the analysis of MK-3. One of the strengths of this method is that it focuses on the randomness of cryptographic primitive function rather than only on the randomness of the output.

Performance and power consumption are key features for evaluating any processor design. In this paper, we present close attention to the impact on power and energy consumption of customized Instruction Set Architecture (ISA) designed by means of High Level Synthesis (HLS) tools. We compare these results against a full ISA soft processor, Microblaze. Our customized ISA processors greatly reduce the power consumption and usage of hardware resources by limiting the implemented instructions to those relevant to specific applications, while still allowing to run the target software kernels. The power estimations are based on the results obtained from the latest Xilinx Vivado Design Suite. After testing our approach on two relevant test benches -a linear algebra application and an encryption application-results reveal that our proposed customized ISA processors consume only 0.5x-0.7x total power and 0.2x-0.6x dynamic power of the fully implemented soft processor with a reasonable performance impact.

Keccak is the hash function selected by NIST as the new SHA-3 standard. Keccak is built on sponge construction, and it provides a new keyed Message Authentication Code (MAC) function called MAC-Keccak. The focus of this work was to apply the power analysis attacks that use Correlation Power Analysis (CPA) technique to extract the secret key. Our attack methodology utilizes simulated power consumption waveforms and is applied to the Keccak high-speed core hardware design from the SHA-3 competition. 1-bit, 2-bit, 4-bit, 8-bit, and 16-bit CPA selection function key guess size attacks are performed on the waveforms to compare and analyze computational effort of successful key extraction on MAC-Keccak. Our experiments confirm that the larger the selection function key guess size is used, the better the fewer traces are needed to retrieve the key, but using more computation time.