This paper introduces advances in the performance of AI and deep learning inference application on the next generation Intel Xeon Scalable processor, code-named Cascade Lake, which also includes support for Intel Optane DC persistent memory, a breakthrough nonvolatile memory technology that bridges the gap between DRAM and storage.

A process for the monolithic integration of enhancement- and depletion-mode high electron mobility transistors (E/D-HEMTs) on InAlAs/InGaAs/InP is reported. The E-HEMTs with a 1.0-μm gate length exhibit a threshold voltage of +255 mV and a maximum dc extrinsic transconductance of 503 mS/mm at room temperature, while a threshold voltage of -317 mV and a transconductance of 390 mS/mm are measured for the D-HEMTs of the same gate length. The devices show excellent RF performance, with a unity current-gain cutoff frequency (ft) of 35 GHz and a maximum frequency of oscillation (fmax) of 95 GHz for both the E- and D-HEMT's. To the best of the authors' knowledge, this is the first demonstration of an E/D-HEMT technology on lattice-matched InP that is suitable for circuit integration

A review of the latest results on high performance Si/SiGe FETs grown on relaxed buffer is presented. A discussion of the fabrication issues facing the achievement of these devices is also included.

As the dimensions of state-of-the art metal-semiconductor-metal photodetectors (MSMPD's) decrease, effects that are insignificant for relatively large geometries become significant in the optoelectronic performance of submicron MSMPD's, Accurate modeling of these effects is necessary to precisely predict the performance of these devices by computer simulation, In this paper, a technique that accounts for the effect of diffraction from a single slot and interference from adjacent interelectrode gaps for front-illuminated MSMPD's is presented, For the purpose of demonstrating the technique, InGaAs MSMPD's illuminated with 1.55-mu m wavelength have been simulated, The results are compared to the conventional shadowed exponential decay model, The new model predicts fundamentally different carrier distribution within the device. This disparity has been observed for devices with electrodes spaced up to 1.5 mu m apart, emphasizing the significance of interference effects even for conventional devices.

The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 /spl mu/m. A maximum extrinsic transconductance (g/sub mext/) of 701 mS/mm and a threshold voltage (V/sub T/) of 167 mV was measured for 0.3 /spl mu/m gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f/sub t/) of 116 GHz was measured as well as a maximum frequency of oscillation (f/sub max/) of 229 GHz for 0.3 /spl mu/m gate-length E-HEMTs.

The authors report the fabrication and characterization of E/D-mode 0.5 /spl mu/m gate-length direct-coupled FET logic (DCFL) inverters, and an 11-stage ring oscillator with a 3-stage output buffer, based on these inverters. Testing of discrete 0.5 /spl mu/m devices gave threshold voltages of 195 mV with a standard deviation of 9 mV for the E-HEMTs, and -365 mV with a standard deviation of 19 mV for the D-HEMTs. RF testing yields unity current gain cutoff frequencies (f/sub t/) of 70 GHz and 67 GHz for the E-HEMTs and D-HEMTs respectively. The inverters were tested for DC performance and the voltage transfer curve shows noise margins of 145 mV at supply voltages as low as 0.6 V. The ring oscillator was tested using a spectrum analyzer and shows propagation delays as low as 20.66 ps/stage, power dissipation as low as 120 /spl mu/W/stage, and power delay products as low as 2.65 fJ/stage. The fabrication process, inverters, and ring oscillator are described in detail.

In this letter, we present results of enhancement and depletion mode transistors fabricated on the same layer structure of Si/SiGe, without using gate recess. The current in the enhancement mode device is controlled by a pn-junction, while that of the depletion-mode device is controlled by a Schottky barrier. A peak transconductance of 327 mS/mm and 417 mS/mm has been achieved in 0.5-mu m gate length depletion and enhancement-mode transistors, respectively.

The fabrication and characterization of an 11-stage ring oscillator utilizing integrated enhancement- and depletion-mode (E/D-mode) high-electron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGaAs/InGaAs material system is demonstrated. The 0.5-mu m gate length depletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V-T) of -365 mV with a standard deviation of 19 mV, while the enhancement-mode HEMT's (E-HEMT's) with identical gate length display a V-T of 195 mV with a standard deviation of only 9 mV. The unity current gain cutoff frequency (f(t)) for both devices is 70 GHz. The extremely high uniformity of the threshold voltages of these devices allowed for the implementation of a ring oscillator utilizing direct coupled FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time (tau(pd)) of 22.4 ps/stage, and a corresponding power dissipation of 120 mu W/stage is measured, yielding a power delay product (PDP) of 2.65 fJ/stage. To the best of the authors' knowledge, this is the first demonstration of a circuit employing E/D-HEMT technology in the lattice-matched InP-based material system.

The impulse response of interdigitated InGaAs metal-semiconductor-metal photodetectors (MSMPDs) is modeled using a two dimensional transit-time calculation coupled with an equivalent circuit model of the intrinsic and parasitic elements of the MSMPDs. The simulated and experimental bandwidths of InGaAs MSMPDs with resistive transparent indium-tin-oxide and low-resistivity opaque titanium/gold electrodes are in excellent agreement and were found to be 6 and 11 GHz, respectively. The electrode width and spacing of these devices are 3 µm and the active area is 2500 µm2. This model aids in the design of MSMPDs with various electrode geometries, electrode materials, semiconductor materials, and methods of illumination.

A detailed study of the performance of monolithically integrated photoreceivers based on metal-semiconductor-metal (MSM) photodetectors (PD's) and HEMT's is undertaken. Two different stacked-layer approaches to integrating MSM-PD's with HEMT's are investigated, and the performance of detectors and HEMT's for each approach is compared. The structure with the MSM layers grown on top of the HEMT layers exhibited the best overall performance. A physics-based MSM model is developed and incorporated into microwave circuit design software; excellent agreement between circuit simulations and measured frequency responses is demonstrated. To evaluate the effects of MSM electrode geometry and detector area on photoreceiver performance, photoreceivers with MSM interelectrode spacings of 1, 1.5, and 2 /spl mu/m were fabricated and characterized. The electrical amplifier used in the photoreceivers is a two-stage, variable-transimpedance amplifier with a common-gate HEMT as the feedback path. By adjusting the DC voltage applied to the gate of this feedback HEMT, transimpedances ranging from 55.8 to 38.1 dB/spl Omega/, with corresponding -3 dB cutoff frequencies from 6.3 to 18.5 GHz, were measured experimentally. Excellent noise performance has been measured, with average input noise current spectral densities of 7.5, 8, and 12 pA/Hz/sup 1/2/ obtained for bandwidths of 6.3, 8, and 13.7 GHz, respectively. A packaged receiver has been tested at 5 Gb/s and an open eye pattern obtained.

The fabrication and performance of ultra-high-speed 0.3-/spl mu/m gate-length enhancement-mode high-electron-mobility transistors (E-HEMT's) are reported. By using a buried platinum-gate technology and incorporating an etch-stop layer in the heterostructure design, submicron E-HEMT devices exhibiting both high-threshold voltages and excellent threshold voltage uniformity have been achieved. The devices demonstrate a threshold voltage of +171 mV with a standard deviation of only 9 mV. In addition, a maximum DC extrinsic transconductance of 697 mS/mm is measured at room temperature. The output conductance is 22 mS/mm, which results in a maximum voltage gain (g/sub m//g/sub 0/) of 32. The devices show excellent RF performance, with a unity current-gain cutoff frequency (f/sub t/) of 116 GHz and a maximum frequency of oscillation (f/sub max/) of 229 GHz. To the best of the authors' knowledge, these are the highest reported frequencies for lattice-matched E-HEMT's on InP.

A metal-semiconductor-metal photodetector (MSMPD) with a hybrid combination of transparent cadmium-tin-oxide and opaque Ti:Au electrodes is proposed and demonstrated. A significant decrease in dark current is obtained by independently engineering the Schottky barrier heights at the anode and cathode. In addition, the use of transparent electrodes enables more light to be coupled into the front-side illuminated MSMPDs thereby increasing the responsivity. For an applied bias of 5 V, these devices exhibited an extremely low dark current density of 21.2 fA/μm2 and a high responsivity of 0.56 A/W to perpendicularly incident 1.31 μm wavelength light.

An InAlAs/InGaAs/InP metal-semiconductor-metal photodetector with engineered Schottky barrier heights has been fabricated. A significant decrease in dark current with no change in the responsivity or the bandwidth was obtained by independently engineering the Schottky barrier heights at the anode and cathode. These photodiodes with an electrode width and spacing of 2 μm exhibited a dark current density of 20.0 fA/μm2 at an applied bias of 5 V. This dark current density is ∼6 times lower than the previously reported minimum.