A design is presented and computer-simulated for high-mobility Si/SiGe heterojunction CMOS transistors. Comparing 0.2 /spl mu/m Si/SiGe FETs to bulk Si FETs, an increase is predicted in current drive of 125% and 23% in the p-FET and n-FET, respectively. For given propagation delay (55 ns), simulated loaded ring oscillators at 1.5 V exhibit 4.6 times reduction in power-delay-product compared to bulk Si CMOS oscillators of the same design rules operating at 2.5 V.

Atomic force microscopy is used to measure surface morphology of modulation doped Si/SiGe heterostructures. Three components in the surface roughness are observed: μm-scale roughness arising from misfit dislocations formed to relieve strain, 1000-Å-scale roughness believed to be associated with three-dimensional growth of the electron or hole channel layers, and atomic-scale roughness with wavelengths of 10–100 Å. Detailed Fourier spectra of the roughness are obtained and used as input to a scattering computation for determining mobility. The results are compared with other mobility-limiting mechanisms, including scattering from ionized impurities and from dislocations.

We report gated Hall effect measurements and the study of electron mobility versus density in high-mobility modulation-doped Si/SiGe heterostructures. Front and back gates have been used to control the electron density and the shape of the electron wave function in the strained Si channel. The gate control on the electron density is modeled using a self-consistent Schrödinger and Poisson equation solution. We find that the electron mobility μ increases with electron density n as μ∝nα, where α is 1.2–1.8 at low n, and 0.7–1.0 at high n. A peak mobility of 5.2×105 cm2/V s at 0.4 K, considerably higher than the value in comparable ungated structures, is achieved when the electron wave function is moved away from the top heterointerface towards the center of the Si channel.