With relentless scaling of transistor dimensions, the single cell soft error rate (SER) reduces with each technology node [1]. InGaAs and Ge complementary FinFET technology is promising for next generation NMOS/PMOS FETs, due to their superior transport properties [2] over silicon, but their soft error performance is unexplored to date. Previous work investigated the SER in InAs nFinFET assuming symmetrical NMOS and PMOS current and exposed the vulnerability of InAs FinFET compared with Si FinFET [3]. In this work, we evaluate the soft error rates in InGaAs n-channel and Ge p-channel FinFETs for complementary logic application.

Coupled oscillators provide an efficient non-Boolean paradigm for solving a variety of computationally intensive problems in computer vision. This motivates the realization of large networks of low-power coupled oscillators. In this work, we experimentally demonstrate: (i) a relaxation oscillator based on the insulator-metal transition (IMT) in vanadium dioxide (VO 2 ) with record low DC input (peak) power of ~23 μW; (ii) a network of coupled VO 2 oscillators with record number of elements (6 oscillators) which perform image processing functionalities in high dimensional space like color detection and morphological operations such as dilation and erosion). Calibrated simulations show that 10× reduction in power compared to a 32 nm CMOS accelerator at iso-throughput.

We experimentally demonstrate and benchmark the performance of p-channel TFETs (PTFETs) comparing Group III-V (In 0.65 Ga 0.35 As/GaAs 0.4 SW 0.6 ) against Group IV (Ge/Ge 0.93 Sn 0.07 ) semiconductor hetero-junctions. This is enabled via gate stack engineering with extremely scaled dielectrics achieving the highest accumulation capacitance density (≥3μF/cm 2 ) on both GaAs 0.4 Sb 0.6 and Ge 0.88 Sn 0.12 channels, respectively. Temperature and electric field dependent I-V measurements coupled with first-principles density functional theory (DFT) based band-structure calculations and analytical modeling based on modified Shockley-Read-Hall formalism, are used to quantify contributions to carrier transport from band-to-band tunneling and trap-assisted tunneling (TAT). GeSn based PTFETs are found to outperform In 0.65 Ga 0.35 As/GaAs 0.4 Sb 0.6 PTFETs benefiting from band-gap engineering (higher I on ) and reduced phonon assisted TAT current (lower D it ).

The measured split capacitance-voltage (CV) characteristics are shown. The combination of an in-situ H2 plasma cleaned GaSb cap with a scaled 4.5 nm thick HfO2 gate dielectric results in higher Cox versus the ex-situ HCl cleaned 1 nm Al2O3/10 nm HfO2 gate stack. Fig. 5 shows the transfer characteristics (ID-VG) of the InAs0.8Sb0.2 QW-MOSFETs with an LG=5 μm. The ON current of the long channel MOSFET is 30 μA/μm with a peak Gm of 100 μS/μm and threshold voltage of -0.2V. The SS slope is calculated to be 215 mV/dec. It is evident that the in-situ H2 plasma clean results in a 35% improvement over similar QW-MOSFET devices that used an ex-situ HCl clean (SS= 350 mV/dec) [1] (Fig. 9). Fig. 5 shows the corresponding output characteristics (ID-VD) exhibiting current saturation at low gate voltages. However, external access resistance dominates ID-VD characteristics at high VG. The access resistance was calculated to be REXT= 5.8 kΩ-μm (Fig. 7). The effective mobility corrected for access resistance as a function of carrier density is shown in Fig. 8. The in-situ H2 plasma processed MOSFET exhibits a peak mobility of 4,000 cm2/Vs which represents an increase of 17.5× over Si NMOSFET. In summary, we have demonstrated a 35% improvement in subthreshold slope for InAs0.8 Sb0.2 QW-MOSFET by using in-situ H2 plasma to create a high quality interface between GaSb and HfO2 over the ex-situ cleaned counterpart The resulting InAs 0.8 Sb 0.2 QW-MOSFET shows 17.5x increase in electron mobility over present day silicon MOSFETs.

Information processing applications related to associative computing like image / pattern recognition consume excessive computational resources in the Boolean processing framework. This motivates the exploration of a non-Boolean computing approach for such applications. In this work, we demonstrate, (i) novel hybrid set of pair-wise coupled oscillators comprising of vanadium dioxide (VO2) metal-insulator-transition (MIT) system integrated with MOSFET; (ii) degree of synchronization between oscillators based on input analog voltage difference; (iii) implementation of hardware platform for fast and efficient evaluation of Lk fractional distance norm (k<;1); (iv) improved quality of image processing and ~20X lower power consumption of the coupled oscillators over a CMOS accelerator.

Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si 0.3 Ge 0.7 buffer are fabricated on 300mm bulk Si substrate with 20nm W Fin and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO 2 /Al 2 O 3 /GeO x gate stack achieving ultrathin EOT of 0.7nm with low D IT and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si 0.3 Ge 0.7 buffer on bulk Si substrate exhibiting peak μ h =700 cm 2 /V s , μ h =220 cm 2 /Vs at 10 13 /cm 2 hole density. The s-Ge FinFETs achieve the highest μ*C max of 3.1×10 -4 F/Vs resulting in 5x higher I ON over unstrained Ge FinFETs.

We demonstrate synthesis of p-channel InSb MOSFET with 1.9% compressive biaxial strain with outstanding room temperature and 150K Hall mobility of 680 cm2/Vs and 2,500 cm2/Vs at hole sheet density of 5x1012 /cm2 and 2.3x1012 /cm2, respectively. The incorporation of an InP layer on top of Al0.35In0.65Sb barrier allows for integration of a high-k dielectric and demonstration of InSb pMOSFET with significantly reduced gate leakage. Parallel conduction limits the on-off ratio of the InSb MOSFET above 150K. Refinement of the InP barrier to reduce interface states and buffer layer to reduce parallel conduction is expected to improve InSb pMOSFET characteristics at 300K.

In conclusion, the authors have reported the highest current density ever achieved for a tunnel junction with a Jρ of 975 kA/cm2. Furthermore, reducing the p-type doping in TD1 by half (TD2) reduced Jρ by 78.5% and doubled the PVCR. These results may be used to calibrate band-to-band tunneling models. The fabrication of sub-micron devices, enabled by E-beam lithography and BCB as an ILD, was key to limiting output current and series resistance. Finally, specific resistivities have been extracted which may be used to compare the use of tunnel junctions as contacts; applications include source/drain regrowth and multi-junction solar cells.

Advances in materials growth techniques are enabling new device concepts, circuit approaches, and system architectures to enhance and extend CMOS technology such as tunneling-based static random access memory and steep subthreshold slope III-V tunneling field effect transistors (TFETs). TFETs are essentially gated Esaki (or backward) diodes operating in the reverse (Zener) direction. Recently, the authors reported on record III-V tunnel diodes fabricated on Si via a technique known as aspect ratio trapping (ART). To the knowledge of the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate. In this study, the authors report on (i) the temperature dependence of these devices, (ii) the insensitivity of tunnel current (forward and Zener) to temperature, and (iii) the absence of mid-gap states in the excess current.

High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n+GaAs/n+InGaAs/p+GaAs Esaki diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm2. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki diodes previously reported.