We demonstrate a high-performance, thermally-robust, C-band GeSi Franz-Keldysh electro-absorption modulator (FK-EAM) featuring a compact 0.5 x 50 μm2 active region on a 300-mm silicon photonics platform. The static electrical and optical performance is experimentally evaluated over wide operating ranges, with wafer-scale results yielding an extinction ratio (ER) of 6.44 ± 0.38 dB and a transmitter penalty (TP) of 9.25 ± 0.15 dB, while the best dies achieve an insertion loss (IL) of ∼ 5 dB, figure-of-merit (FOM = ER/IL) of 1.23, and TP of 8.8 dB at λ = 1550 nm under a 2 V peak-to-peak drive, representing the best reported EAM performance. The temperature-dependent measurements from 25-85 ∘C show a monotonic red-shift rate of 0.8 nm/∘C, while maintaining stable performance with ER > 6 dB, FOM > 1, and TP ∼ 9-10 dB across the wafer, demonstrating temperature-robust modulation performance comparable to state-of-the-art room-temperature EAMs. Furthermore, robust EAM operation beyond the nominal design window (∼1590 nm) is sustained even at 85 ∘C. These results establish GeSi EAMs as a key enabling technology for high-speed, low-power, dense silicon-photonic transceivers, operating reliably in thermally exposed dynamic environments, paving the way for next-generation optical I/O applications.

Electron spin resonance spectroscopy (ESR) of a single electron in planar Si-MOS quantum dot is reported in the vicinity of a valley level anti-crossing. A number of one and two-photon resonances are observed due to mixing of magnetic spin-flip and electric valley-flip transitions. This allows the reconstruction of the energy-level diagram of a four state system with two valley and two spin states. Near the anti-crossing, an enhancement of the Rabi frequency is observed. This is attributed to an electric-dipole transition activated by admixing of the upper energy level due to inter-valley spin coupling. The electric-dipole transition may be driven via capacitive coupling between the ESR antenna, and the confinement gate. To characterize spin-valley coupling responsible for the enhancement, we measure the anisotropy of the g-factor difference between the two valley states, the mean g-factor and the inter-valley spin coupling for both in and out-of-plane magnetic fields. The inter-valley spin coupling is strongly modulated by the direction of the B-field, and is strongest for out-of-plane B-field, consistent with an in-plane spin-valley field. In principle, this strong Electric dipole spin resonance (EDSR) effect could be utilized for fast all-electrical spin control in small-scale devices.

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

Scandium-based silicides have attracted attention as new contact materials for ultimately scaled CMOS devices. Excellent contact properties in combination with P-doped Si have been demonstrated. However, unlike conventional Ti, Co, and Ni silicides, little is known about the formation mechanisms and properties of Sc silicides. This manuscript, therefore, reports on the formation and structural properties of orthorhombic ScSi silicide formed by solid state reaction between a sputter deposited 15 nm Sc film and a Si(001) substrate. Synchrotron x-ray diffraction (XRD) pole figures, in combination with cross-sectional transmission electron microscopy, are leveraged to determine the texture of ScSi. An epitaxial texture with two different components is evidenced. Large (≳20 nm) grains, having a minimal defectivity originating from the lattice mismatch between the silicide and the substrate, are distinguished from small (≲5 nm) nanotwinned grains. The formation of these two sets of grains is investigated by in situ XRD. Due to a solid state amorphization reaction between Sc and Si, the formation of orthorhombic ScSi is preceded by the formation of an amorphous ScSi phase. Orthorhombic ScSi formation is initiated at ∼320 °C by the crystallization of small nuclei at the interface with Si, as evidenced for the first time by cross-sectional transmission electron microscopy. These nuclei share a singular epitaxial orientation, corresponding to the one of the large grains in the final ScSi film. Further crystallization occurs anisotropically in the lateral direction. Along the c axis, the initial epitaxial orientation is maintained. However, along the a axis, twin defects are generated, resulting in the small grain size.

We demonstrate up to 180 GBaud PAM4 data transmission below the HD-FEC BER threshold in the O- and C-band using Ge-on-Si APDs with respectively 70 and 100 GHz BW, and 2 and 1.5 A/W responsivity.

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T 2 * up to 41(2) μs and Hahn-echo coherence times T 2 Hahn up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100

Yttrium (Y) is a promising candidate for low-resistance NMOS contacts due to the low n-type Schottky barrier height of its silicide and its high charge carrier effective mass. However, previous attempts to achieve a low contact resistivity have failed because of severe oxygen contamination during sputter deposition. This study therefore investigates Y silicide formation in sputtered TiN/Y stacks on Si(001), Si(110), and Si(111) substrates. Upon annealing, hexagonal YSi1.7 forms through a three-step process: (i) metallic Y reacts with Si by solid-state amorphization (SSA), producing amorphous a-YSi, (ii) a-YSi crystallizes into hexagonal YSi1.7 at the interface with Si and (iii) grows in thickness until the reaction is fully completed. X-ray diffraction pole figure analyses confirm epitaxial texturing, with Si(001) and Si(111) exhibiting a single epitaxial component. Consistent with a nucleation-controlled formation, hexagonal YSi1.7 starts to form at a significantly lower temperature on Si(111) compared to Si(001) and Si(110) due to the superior YSi1.7/Si epitaxial relationship. The formation of pinholes during crystallization further supports nucleation-limited formation but results in a partial oxidation of the Y film. These findings clarify the role of nucleation and diffusion during YSi1.7 formation and highlight the challenges that must be addressed should Y be integrated in CMOS devices.

Scandium (Sc) silicides, formed through solid-state reactions between thin Sc films and Si, have recently gained attention for their potential in low-resistance metal/semiconductor contacts. In this work, in situ x-ray diffraction is used to investigate the phase evolution of Sc thin films deposited on Si(001), Si(110), and Si(111) substrates. As-deposited, Sc crystallizes in the hexagonal P6(3)/mmc structure, while a thin amorphous silicide interlayer exists at the Sc/Si interface. Upon annealing, this interlayer thickens via a solid-state amorphization reaction between Sc and Si. At higher temperatures, orthorhombic ScSi nucleates at the interface, while residual Sc transforms into the metastable P6(1)22 hexagonal phase before fully reacting. The formation of orthorhombic ScSi from the amorphous precursor phase is nucleation-controlled. As a result, the crystallization temperature, textural disorder, and interface roughness depend on the Si substrate orientation. On Si(001) and Si(111), ScSi exhibits multiple epitaxial texture components associated with smooth interfaces. In contrast, Si(110) shows the highest crystallization temperature, a rough interface, and a highly disordered axiotaxial texture. Surprisingly, this axiotaxy occurs despite the absence of one-dimensional lattice matching between the film and the substrate.

We report on the design, modeling, and measurements of high-speed, silicon-contacted, waveguide-coupled Germanium-on-Silicon (Ge/Si) avalanche photodiodes (APDs) fabricated on 300 mm Silicon On insulator (SOI) wafers. The devices achieve a peak 3-dB bandwidth (BW) exceeding 100 GHz and maintain 70 GHz BW at a responsivity of 2 A/W in both the O- and C-bands, at a relatively low reverse bias of 7 V. These results demonstrate the strong potential of Ge/Si APDs to be used for next-generation short-reach optical interconnects targeting 400 Gbps per lane operation.

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the field-programmable gate array embedded in Keysight's Quantum Engineering Toolkit, the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

The rate of coherence loss is lower for a qubit under the Rabi drive than a freely evolving qubit T-2(Rabi )> T-2(& lowast;) . Building on this principle, concatenated continuous driving (CCD) keeps the qubit under continuous drive to suppress noise and manipulate dressed states by either phase or amplitude modulation. In this work, we propose a variant of CCD which simultaneously modulates both the amplitude and phase of the driving field to generate a circularly polarized field in the rotating frame of the carrier frequency. This circular-modulated CCD (CMCCD) cancels the counterrotating term in the second rotating frame, eliminating a systematic pulse-area error that arises from an imperfect rotating wave approximation for fast gates. Numerical simulations demonstrate that the proposed CMCCD achieves higher gate fidelity than conventional CCD schemes. We further implement and compare different CCD protocols using an electron spin-qubit in an isotopically purified Si-28-MOS quantum dot and evaluate its robustness by applying static detuning and Rabi frequency errors. The robustness is significantly improved compared with the standard Rabi drive, showing the effectiveness of this scheme for qubit arrays with variation in qubit frequency, coupling to the Rabi drive, and low-frequency noise. The proposed scheme can be applied to various physical systems, including trapped atoms, cold atoms, superconducting qubits, and NV centers.

Ge photodiodes deeply recessed into highly doped Si are fabricated, reducing series resistance, transit time and diffusion. Bandwidths exceeding 110 GHz with 0.9 A/W responsivity were measured, with ≤ 6fF capacitance at -0.5 V bias.

We report the recent progress of waveguide-coupled O-band GeSi quantum confined stark effect electroabsorption modulators, monolithically integrated in a Si photonics platform on 300 mm Silicon-on-insulator wafers with 220 nm thick Si top layer. A wafer-scale analysis of static insertion loss (IL) and extinction ratio (ER) is presented, showing IL down to 7.5 dB with ER of 5 dB for a 36.8 mu m long device, at drive voltages of 2 V peak-to-peak. Modulation bandwidths beyond 50 GHz are demonstrated, with an extracted junction capacitance of 57 fF and series resistance of 8.3 Omega. Finally, open eye diagrams are demonstrated for non-return-to-zero on-off keying (NRZ-OOK) modulation for data rates from 40 Gb/s up to 64 Gb/s, with dynamic extinction ratio of 2.5 dB, at 1320 nm wavelength.

This paper demonstrates the relevance of X-rays for inline metrology and process control of complementary field-effect transistors (CFET). After briefly reviewing the stringent metrology needs of CFET, we focus on the starting epitaxial SiGe/Si multilayer and demonstrate that inline X-ray diffraction (XRD) allows the accurate measurement of every individual thickness and composition of this complex stack. Further, we compare to the performance of inline X-ray reflectivity (XRR), which beyond providing individual thicknesses in angstrom-level agreement with XRD also gives access to elusive information about the roughness of the SiGe/Si interface. Moving along the integration flow, we explore the profiling capabilities of inline grazing-incidence small-angle X-ray scattering (GI-SAXS) after inner spacer lateral recess through simulation and preliminary experiments. As we demonstrate, GI-SAXS provides independent information about width, height and inner spacer cavity depth but would necessitate deeper probing depths and smaller beam footprint to enable CFET metrology. Moving to incident energies lower than the currently used Cu K alpha might solve this issue.

The realisation of an universal quantum computer will require the operation of thousands to millions of qubits. The possibility of using existing industrial semiconductor fabrication techniques and infrastructure for up-scaling and reproducibility makes silicon based spin qubits one of the most promising platforms to achieve this goal. The implementation of the up to now largest semiconductor based quantum processor was realized in a silicon/silicon-germanium heterostructure known for its low charge noise, long qubit coherence times and fast driving speeds, but the high structural complexity creates challenges for industrial implementations. Here we demonstrate quantum dots hosted in a natural Si/SiGe heterostructure fully fabricated by an industrial 300mm semiconductor wafer process line from heterostructure growth to Co micromagnet monolithic integration. We report charge noise values below 2μ eV/√(Hz), spin relaxation times of over 1s and coherence times T_2^* and T_2^H of 1μ s and 50μ s respectively, for quantum wells grown using natural silicon. Further, we achieve Rabi frequencies up to 5MHz and single qubit gate fidelities above 99%. In addition to scalability, the high reproducibility of the 300mm processes enables the deterministic study of qubit metric dependencies on process parameters, which is essential for optimising qubit quality.

Transmission electron microscopy (TEM) and related characterization techniques are widely used to inspect semiconductor devices. Conventional TEM (CTEM) and scanning TEM (STEM) methods mostly keep the incident electron beam at a fixed angle, aligned with the optical axis of the electron microscope. While effective in many scenarios, this invariance could limit the potential for more complex applications. We investigate a technique that allows us to acquire multidimensional data from a series of beam tilt angles. The acquired data can be further processed to provide more information and to reduce the possible errors associated with single data sets. In this paper, we demonstrate the advantages of this technique through several semiconductor use cases. These benefits include reducing unwanted background information in electric field mapping on a SiC film, enhancing strain mapping quality on a Si-SiGe multilayer structure and improving grain mapping on a 3D-NAND device. This beam-tilt technique can be executed via an automated script once the experimental conditions are optimized, paving the way for large-volume investigation through automated TEM.

A latch-up bipolar junction transistor (BJT) selector device for memory crossbar architecture was fabricated using p(+)-Si Ge-1-x ( x) as floating base sandwiched between n+-Si layers. The Ge concentration in the SiGe layers has varied between 25% and 40% and the base thickness between 25 and 35nm. The stack was etched with diameter of the device varied from 50 to 150nm. Finally, the devices were encapsulated using different materials. By using end of line (EOL) high-pressure (HP) H-2 annealing, the latch-up voltage ( V-on) reduced from 2.75 to 2.2V (for 150-nm device diameter) and the nonlinearity (NL = ratio of currents at V-on+100 mV and that at the half of operating voltage) improved from 10(4) to 3x10(4) . This behavior was also studied by 1-D technology computer aided design (TCAD) simulation by introducing traps in the device. Traps at the floating base cause loss of hole, resulting in increased latch-up voltage and elevated leakage current. AlO (x) and SiN (x) offer superior passivation to deposited SiO2, enhancing device performance. The device demonstrates excellent performance, achieving a low Von of 2.2 V, exceptional endurance exceeding 10(10) cycles (under 0-3 V stress for 100 ns), and a high on-state current density of 14MA/cm(2) at 3 V. The results demonstrate the viability of the fabricated n-type/p-type/n-type (NPN) device as a high-endurance selector for crossbar memory architectures.

We demonstrate a 2 km 160 GBd PAM-4 O-band link with traveling-wave drivers and TIAs co-packaged with a new high-responsivity 100 GHz Ge photodetector and transfer printed TFLN MZMs on a silicon photonics platform. ©2025 The Author(s)

Among the many types of qubit presently being investigated for a future quantum computer, silicon spin qubits with millions of qubits on a single chip are uniquely positioned to enable quantum computing. However, it has not been clear whether the outstanding high-fidelity operations and long coherence times shown by silicon spin qubits fabricated in academic settings1-8 can be reliably reproduced when the qubits are manufactured in a semiconductor foundry9-11. Here we show precise qubit operation of silicon two-qubit devices made with standard semiconductor tooling in a 300-mm foundry environment. Of the key metrics, single- and two-qubit control fidelities exceed 99% for all four devices, and the state preparation and measurement fidelities reach up to 99.9%, as evidenced by gate set tomography. We report spin lifetime and coherence up to T1 = 9.5 s, T 2 * = 40.6 μ s and T 2 Hahn = 1.9 ms . We determine that residual nuclear spin-carrying isotopes contribute substantially to operational errors, identifying further isotopic purification as a clear pathway to even higher performance.