The effects of heavy-ion irradiation on 3-D NAND flash memory cells are investigated. Threshold voltage distributions are studied before and after exposure, as a function of the linear energy transfer, fluence, and irradiation angle. Shifts are smaller in 3-D devices than those in planar ones, for the same equivalent bit density. The cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate make it possible to gain insight into the underlying upset mechanism, which cannot be obtained with planar devices. Evidence that energy deposition in the blocking oxide layer can contribute to charge loss from the floating gate is presented.

In this work, we present clear experimental results pointing to a new microscopic picture for cycling-induced charge trapping/detrapping in Flash memories. In particular, the evidence gathered from experiments designed to investigate the dependence of charge detrapping on cell threshold-voltage reveals that the simple and widely used model based only on carrier exchange between oxide defects and substrate is not enough to explain the main features of the phenomenon. We then propose a new microscopic description of the detrapping phenomenology, including structural relaxation of oxide defects as a limiting step enabling carrier exchange. This new microscopic picture for the oxide defects is, finally, implemented in a statistical model able to reproduce the charge trapping/detrapping dynamics and the consequent threshold-voltage instabilities along the memory array lifetime.

Flash memories based on the floating gate architecture are sensitive to ionizing radiation at sea level, including atmospheric neutrons and alpha particles. No data are available on the sensitivity of Flash memories to muons. These particles, although very lightly ionizing, are the most abundant at sea level and have been reported to cause upsets in advanced SRAMs through direct ionization. The purpose of this contribution is to present the first experimental investigation of single event upsets induced by muons in 16-nm NAND Flash memories, using accelerated tests. The experimental results are discussed in terms of threshold voltage shifts and raw bit errors and the threshold LET values are analyzed for advanced samples. We show that muon-induced upsets are indeed possible also in Flash memories, even though the error rate is very low and ECC can easily cope with it.

A 2D 16nm planar NAND cell technology is described with good cell to cell interference and reliability that can be used in a wide variety of applications. This second generation planar cell uses a high-K dielectric stack and a thin poly floating gate to maintain the needed gate coupling ratio and reduce adjacent cell interference. The technology includes select gates with the same planar structure as the cell. This select gate architecture simplifies the manufacturing of this NAND technology.

We present a semi-analytical model for the description of charge trapping and detrapping phenomena occurring during cycling and idle periods in NAND Flash memories. The model is based on a statistical distribution of detrapping time constants that is affected by the composition of cycles and idle periods and accounts for charge discreteness, statistical charge capture and emission and statistical distribution of the threshold-voltage shift due to single detrapping events. The model can reproduce the experimental data under different conditions and allows to develop and monitor accelerated schemes able to mimic realistic on-field usage of the memory device.

This work investigates cycling-induced threshold-voltage instabilities in nanoscale NAND Flash cells as a function of the array background pattern. Instabilities are mainly the result of charge detrapping from the cell tunnel oxide during post-cycling idle/bake periods and represent one of the major reliability issues for multi-level devices. Results reveal, first of all, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. This new interference effect is shown to decrease in magnitude for higher threshold-voltage levels of the victim cell and to come mainly from an interaction with aggressor cells in the bit-line direction. From this evidence, a physical picture explaining the phenomenon and its main dependences is provided.

Flash memories operating in space are subject at the same time to the progressive accumulation of total ionizing dose and to intrinsic aging phenomena. In this work we investigate latent Total Ionizing Dose (TID) effects in 41-nm NAND single level cells that do not display neither floating gate errors nor any apparent kind of degradation after exposure. Retention of irradiated cells is analyzed at room and high temperature as a function of total dose previously received. We found that FG cell retention at room temperature is practically unchanged after a total dose up to 30 krad(Si). On the contrary, TID exposure slightly worsens the cell retention time during high-temperature tests. We attribute this behavior to the removal of compensating electrons from the tunnel oxide at high temperature.

We investigate the effects of X-ray exposure in 41-nm single level NAND Flash memories at small doses, comparable to those used in printed circuit board inspections. We analyze both short-term effects, such as cell threshold voltage shifts during irradiation, and retention and endurance performance of devices exposed to x rays. For doses smaller than 1krad(Si), no effect is observed. At higher doses, charge loss is observed after the exposure and a modest read margin degradation is seen during high-temperature retention tests.