In this letter, we report clear experimental evidence of the existence of a turnaround in the temperature dependence of RTN in 3D NAND Flash memories, showing up when entering the cryogenic regime. The origin of this phenomenology is traced back to the change of the dominant transport mechanism through the grain boundaries of the polysilicon channel of the memory cells, from thermionic emission to quantum-mechanical tunneling. This change decreases the impact of the charging/discharging of microscopic defects at the grain boundaries on cell current, making RTN in the cryogenic regime much more bearable than what expected from the extrapolation of room temperature data.

We present an investigation on the impact of device edge termination on Time-Dependent Dielectric Breakdown (TDDB) in galvanic isolators based on polymeric dielectrics. By means of experimental and numerical analyses, we highlight that electrode thickness and device passivation are important design elements to limit the impact of electric field intensification at device on TDDB and prolong device lifetime. Results point out key aspects to consider to push the performance and the reliability of modern galvanic isolators to their ultimate limits.

In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D NAND Flash memories with polysilicon channel. In Part I we focus on threshold voltage $({\mathrm { V}}_{\mathrm { T}})$ fluctuations induced by traps and show that lower values for the average and rms ${\mathrm { V}}_{\mathrm { T}}$ arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.

We present an analytical model to reproduce the non-monotonic temperature dependence of Time-Dependent Dielectric Breakdown (TDDB) in galvanic isolators based on polymeric dielectrics. The model is based on the concurrent action of two competing mechanisms involved in the TDDB dynamics, namely the worsening of the polymer dielectric strength due to moisture and the outdiffusion of water molecules during the electrical stress phase. By catching the most relevant features of the temperature dependence of TDDB in a simple yet effective way, the model represents a valuable tool to support the design of galvanic isolators based on polymeric dielectrics.

In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D nand Flash memories with polysilicon channel. In Part I we focus on threshold voltage (VT) fluctuations induced by traps and show that lower values for the average and rms VT arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells.

In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D nand Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.

We present an investigation that relates the dynamics of Time-Dependent Dielectric Breakdown (TDDB) in polymeric dielectrics for galvanic isolators to the moisture content of the materials. The analysis is based on experimental data for the temperature activation of both TDDB and moisture absorptionloutdiffusion in the devices. The observed phenomenology is explained through a solid physical picture, which is quantitatively supported by a simple-yet-effective model for the moisture-driven dynamics of TDDB. Results point out primary aspects to consider when assessing the reliability of galvanic isolators based on polymeric dielectrics under real on-field operating conditions.

In this letter, through experimental evidence collected at room temperature and in the deep-cryogenic regime, we demonstrate that the so-called vertical charge loss from the gate stack of 3-D charge-trap NAND Flash memories is a process featuring widely distributed time constants. Results reveal that the turn-on of these time constants depends on the temperature at which the program operation is carried out. This, combined with the dependence of the time constants on the temperature at which vertical charge loss is monitored, gives rise to an apparent activation energy of the cell threshold-voltage transient during data retention that is close to zero when data retention and program occur at the same temperature. This phenomenology must be carefully taken into account when trying to extend the working temperature of NAND Flash memories down to the deep-cryogenic regime.

In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D NAND Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.

In this article, we report the first experimental investigation of the behavior of the 3-D NAND Flash memory technology in the deep-cryogenic regime (temperature T < 50 K). Clear evidence is provided to demonstrate that, in that T regime, the reduction of the Read bitline voltage gives rise to a paradigm shift in the current-voltage characteristics of the memory cells, consisting of the appearance of single-electron transistor (SET)-like conduction schemes. The phenomenon is traced back to nonuniformities in the electrostatic inversion of cell channel, producing, at that deep-cryogenic T, a landscape of conductive quantum dots separated by energy barriers where electron transport is affected by Coulomb blockade. The results represent a first step toward innovative applications of 3-D NAND Flash memories.

In this paper, we report clear experimental evidence proving that programmed cells in a 3D NAND Flash memory array may experience an unexpected average increase in their threshold voltage (VT) during high-temperature data retention. The phenomenon is explored as a function of the VT level of the monitored cells, the string back-pattern, and the data-retention temperature. A physical picture is then proposed to explain its origin, which is traced back to the depassivation of some traps in the polysilicon channel of the 3D NAND strings. Results point out a new reliability issue to address and tackle in the design of next generation 3D NAND Flash technologies.

In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms give rise to threshold-voltage $(\mathbf {V_{T}})$ instabilities with similar activation energy and comparable magnitude on fresh devices. On the other hand, polysilicon trap depassivation displays a negligible strengthening with cycling and a more marked dependence on the cell $\mathbf {V_{T}}$ level during data retention with respect to charge detrapping. Results must be carefully considered in the reliability assessment of all state-of-the-art and future 3D NAND Flash technology nodes.

In this work, by means of 3D TCAD simulations, we analyze the effects of the trap-induced percolative conduction in the polysilicon channels of 3D NAND memory cells. We demonstrate that the discrete nature of traps at polysilicon grain boundaries affects the memory cell threshold voltage and its fluctuation, as well as the random telegraph noise, with larger impact than is predicted by a continuous-trap approach. Our results highlight the importance of discrete-trap modeling for accurate variability prediction.

We present a detailed analysis of the time dynamics of the down-coupling phenomenon (DCP) in 3-D NAND Flash memory strings. The transient time dynamics of the channel potential following the wordline (WL) bias transition from the pass voltage to zero is studied via numerical simulation, highlighting the existence of three temporal regimes controlled by different physical processes: electron emission from traps, hole injection from the string edges followed by capture, and propagation along the string. The impact of these processes is separately studied, followed by an analysis of the dependence of the DCP recovery time on architectural parameters. Results highlight the relevant physics and can be used as a design guideline for NAND strings with reduced sensitivity to the DCP.

In this paper, we report a comprehensive modeling investigation of the Pt/BaTiO3/Nb:SrTiO3 stack designed to operate as a Ferroelectric Tunnel Junction (FTJ). The analysis accounts for some specific features of the materials in the stack that are typically overlooked, such as the electric field dependence of the dielectric constant of Nb:SrTiO3 and the dependence of the dielectric constant of BaTiO3 on its thickness. Modeling results are validated through a systematic and consistent comparison with experimental data for the current–voltage characteristics of devices with different stack parameters, at different temperatures. From that, the resistive memory window of an FTJ based on the Pt/BaTiO3/Nb:SrTiO3 stack is then explored over its design space. Results allow to comprehensively assess the ultimate performance of the device, providing hints for the successful development of next-generation FTJ-based memory technologies.

In this letter, we present clear experimental evidence proving that a high-temperature idle/data-retention phase gives rise to a permanent intensification of random telegraph noise (RTN) in 3-D NAND Flash arrays. The magnitude of RTN intensification is shown to be strongly dependent on the threshold-voltage level on which cells spent the high-temperature phase and to be independent of the backpattern of the NAND string. The effect is explained in terms of depassivation of some traps at the grain boundaries of the polysilicon channel of the memory cells during the high-temperature phase, leading to stronger nonuniformities in channel inversion and to a higher number of defects active in the RTN process. The reported phenomenology represents an addition idle/data-retention issue and another constraint to the noise margins of 3-D NAND Flash arrays.

The transition from planar (2D) to three-dimensional (3D) arrays represented a turning point for the phenomenology of random telegraph noise (RTN) in NAND Flash technologies. The relevant changes in the cell structure and in the process integration at the basis of that transition, in fact, strongly impacted some major aspects of the physics responsible for RTN and for its dependence on the array working conditions. In this paper, we comprehensively discuss the recent advances in the exploration and in the understanding of such physics in 3D arrays. The discussion allows us to identify the most relevant details related to array operation, which must be addressed to mitigate the reliability issues arising from RTN, contributing to the attempt to prolong the successful evolutionary trends of 3D NAND Flash technologies.

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

This paper covers the recent evolution of high-density solid-state storage, which is the most prominent storage solution of the 21st century. The attention is focused on the two integrated technologies that more than any other are revolutionizing the storage landscape: the NAND Flash technology and the Phase-Change Memory (PCM) technology. The success of the NAND Flash technology has been the outcome of its strenuous attempt not only to maximize the bit storage density achievable with a cost-effective process over the surface of a silicon die, but also to increase that density at a regular pace thanks to favorable evolutionary approaches. In this way, NAND Flash memories have become the elective storage media for a wide variety of electronic applications, overwhelming hard-disk drives. The PCM technology represents, instead, a notable exploitation of a new memory concept to provide a novel trade-off among cost, performance and reliability. In particular, the PCM attempt to address performance more than cost needs is driving a shift in the traditional storage hierarchy, with storage-class memory finally becoming a reality.