The effects of heavy-ion irradiation on 3-D NAND flash memory cells are investigated. Threshold voltage distributions are studied before and after exposure, as a function of the linear energy transfer, fluence, and irradiation angle. Shifts are smaller in 3-D devices than those in planar ones, for the same equivalent bit density. The cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate make it possible to gain insight into the underlying upset mechanism, which cannot be obtained with planar devices. Evidence that energy deposition in the blocking oxide layer can contribute to charge loss from the floating gate is presented.

The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.

The aim of this work is to investigate the physical mechanisms behind TANOS (TaN/Alumina/Nitride/Oxide/Silicon) cycling degradation. A comparison of the degradation induced in the TANOS stack by unipolar or bipolar stress has allowed the separation the different degradation contributions. A comparison with standard floating gate (FG) stack has also been carried out to confirm these degradation mechanisms. Finally, different stack configurations are reported, showing the key factors affecting the degradation and giving trends for improving cycling degradation.

The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore's law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials.NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect.. thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um(2) at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate.In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.

This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.