Quantum computing relies on the operation of qubits in an environment as free of noise as possible. This work reports on measuring the impact of environmental radiation on lifetimes of fixed frequency transmon qubits with various capacitor pad geometries by varying the amount of shielding used in the measurement space. It was found that the qubit lifetimes are robust against these shielding changes until the most extreme limit was tested without a mixing chamber shield in the refrigerator. In contrast, the quasiparticle tunneling rates were found to be extremely sensitive to all configurations tested, indicating these devices are not yet limited by losses related to superconducting quasiparticles.

We describe design, implementation, and performance of an ultra-high vacuum (UHV) package for superconducting qubit chips or other surface sensitive quantum devices. The UHV loading procedure allows for annealing, ultra-violet light irradiation, ion milling, and surface passivation of quantum devices before sealing them into a measurement package. The package retains vacuum during the transfer to cryogenic temperatures by active pumping with a titanium getter layer. We characterize the treatment capabilities of the system and present measurements of flux tunable qubits with an average T1 = 84 µs and T2 echo=134μs after vacuum-loading these samples into a bottom loading dilution refrigerator in the UHV-package.

One of the main limitations in state-of-the art solid-state quantum processors are qubit decoherence and relaxation due to noise in their local environment. For the field to advance towards full fault-tolerant quantum computing, a better understanding of the underlying microscopic noise sources is therefore needed. Adsorbates on surfaces, impurities at interfaces and material defects have been identified as sources of noise and dissipation in solid-state quantum devices. Here, we use an ultra-high vacuum package to study the impact of vacuum loading, UV-light exposure and ion irradiation treatments on coherence and slow parameter fluctuations of flux tunable superconducting transmon qubits. We analyse the effects of each of these surface treatments by comparing averages over many individual qubits and measurements before and after treatment. The treatments studied do not significantly impact the relaxation rate $\Gamma_1$ and the echo dephasing rate $\Gamma_2^\textrm{e}$, except for Ne ion bombardment which reduces $\Gamma_1$. In contrast, flux noise parameters are improved by removing magnetic adsorbates from the chip surfaces with UV-light and NH$_3$ treatments. Additionally, we demonstrate that SF$_6$ ion bombardment can be used to adjust qubit frequencies in-situ and post fabrication without affecting qubit coherence at the sweet spot.

The resistivity of damascene Cu is measured at cross-sectional area as low as 95 nm 2 . The impact of aspect ratio and line edge roughness on resistivity is investigated. Kelvin resistance test structures are demonstrated with 28 nm pitch wires patterned by directed self-assembly of lamellar block copolymers. The effective resistivity of TaN/Ta/Cu wires is compared with alternative metals.

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm 2 . Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.

We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can be integrated to density targets commensurate with CMOS scaling needs of the 10 nm node and beyond. In addition, this work achieves the highest performance for GAA SiNW NFETs at a gate pitch below 100 nm.

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.