P-i-N and Schottky P-i-N diamond diodes are a promising technology for high-power limiters. Receivers, solid-state amplifiers, and detectors commonly use P-i-N and/or Schottky diodes for protection from high power incident signals. Here, we report on the RF power handling and power dissipation capability of diamond P-i-N and Schottky P-i-N diodes. We fabricate P-i-N diodes as vertical structures, with both majority and minority carriers involved in charge transport. Similarly, we fabricate vertical Schottky P-i-N diodes, with the doping in the n-layer reduced compared to P-i-N diodes such that the n-layer becomes fully depleted during operation, resulting in a majority-carrier device with a fast recovery time. Both P-i-N and Schottky P-i-N diodes were packaged in shunt-configuration and matched for 3 GHz operation, with a small signal insertion loss of ∼1.25 dB. P-i-N diodes operated up to 40 dBm before failing nondestructively at 45 dBm, demonstrating power dissipation handling that exceeds that of commercially available Si P-i-N diodes by more than a factor of five. Schottky P-i-N diodes operated up to 49 dBm before non-recoverable failure at 50 dBm.

We report on the development of the super-lattice castellated field effect transistor (SLCFET) technology as a candidate for the next generation of mmW and $W$ -band systems, leveraging the high carrier density and a high degree of charge control offered by this device topology for mmW and $W$ -band power amplification. The SLCFET is built using a superlattice of stacked AlGaN/gallium nitride (GaN) heterostructures that are etched into nanoribbons between epitaxial regrown n+ GaN source and drain contacts and controlled with a 100 nm length T-gate that electrostatically actuates the stacked channels from the sidewalls. The $2\times 20\,\,\mu \text{m}$ amplifier cells of SLCFET devices were measured using load–pull at 94 GHz using a 12-V bias, demonstrating amplifier output power densities of 10.87 W/mm with 43% power added efficiency (PAE) at peak power and a maximum linear gain of 5.4 dB. The SLCFET amplifier process attains this power density due to its extremely high current density, with an IMAX of 4.8 A/mm, along with its minimal dispersion, with current collapse measured using pulsed $I$ – $V$ at < 7%. The SLCFET technology, with its previously demonstrated world-class RF switch performance and now record $W$ -band amplifier performance, is ideal for use in next-generation mmW and $W$ -band systems.

The super-lattice castellated field-effect transistor (SLCFET) is a multi-channel AlGaN/GaN HEMT device emerging as a technology platform for RF front ends, integrating world-class RF switches with high-performance RF amplifiers on the same wafer. This paper reports the performance results of a SLCFET amplifier device using an ALD TiN T-gate, which are improved with respect to previously reported data, with measured f t and f max up to 99 and 152 GHz respectively. The improvement is attributed to a reduced gate capacitance due to a higher T-gate hat without significant penalty of loss in gate control or increase of gate resistance. We also report W-band (94 GHz) large signal load-pull performance of the device with 4.33 W/active mm output power and 19.2% PAE. The process also demonstrates excellent DC/RF dispersion gate lag <1% and drain lag <2% and high breakdown voltage of 55 V.

The Millimeter-Wave Scalable Unconstrained Broadband Array (MMW SCUBA) system leverages cutting edge chip integration, additive manufacturing, and packaging technology to realize an 18–50 GHz, dual-polarized, scalable phased array antenna with element-level digital beamforming. We report on the demonstration and test of a 16 element free-space-to-RF prototype, as well as progress on the development of a larger 64 element array prototype build which extends integration from free-space to digits.

We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in OFF-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements.

This paper reports frequency performance improvements in Superlattice Castellated Field Effect Transistor (SLCFET) amplifier through device scaling. Device scaling incorporates the variations in castellation ridge width, castellation trench width, castellation length, gate stem length, gate hat length, gate offset, gate dielectric thickness, and passivation thickness. Highest ${f_{T}}$ and Fmax (70GHz/150GHz) values were achieved on devices with shortest castellation length. Shortening castellated access region reduces series resistance resulting in improved frequency performance. Thinner gate dielectric improves transconductance resulting enhancement in frequency performance as well.

On behalf of myself and my fellow Guest Editors for the Special Issue on Ultra Wide Band Gap Semiconductors for Power Control and Conversion appearing in this month’s issue of the IEEE Transactions on Electron Devices, we are gratified to be able to present readers with a selection of papers spanning the current state of the art in wide and ultrawidebandgap semiconductor devices. Electronics for power control and conversion is presently going through a renaissance, with new device concepts, extensions of known concepts to new materials, and new applications all merging simultaneously. Fundamental material-level work in Ga 2 O 3 , diamond, Al(Ga)N, and other ultrawidebandgap materials have begun to produce device results commensurate with the fundamental advantages that these materials promise for power control and conversion applications. At the same time, the understanding and performance of devices based on SiC and GaN continue to improve. Applications of these new materials and devices include automotive, data center power management, grid control, industrial and locomotive traction control, and others. Despite the tremendous progress in this area, however, much remains to be understood. The role of intrinsic and extrinsic defects in these materials on device performance, optimal strategies for device design and fabrication, surface passivation, and dielectric materials suitable for the high electric fields supported by these materials, device structures, and concepts for achieving the best possible electrical performance, appropriate approaches to thermal management, and the potential and challenges of integration of these devices with other semiconductors for system implementation are all areas in which rapid progress is being made.

Efficient, high power density RF signal amplification is a driving enabler for future RF systems. The Super-Lattice Castellated Field Effect Transistor (SLCFET) leverages a GaN-based superlattice to support multiple stacked 2D-Electron Gas (2DEG) layers, thereby increasing its charge density compared to conventional GaN transistors by as much as 10x, directly boosting output power density. The low sheet resistance of the stacked 2DEG superlattice layers lowers device contact and source resistances, resulting in a low knee voltage. In addition, the SLCFET uses a three-dimensional, low resistance gate electrode to maintain healthy device electrostatics, high output resistance, and low input resistance. With these advantageous device characteristics, the SLCFET RF amplifier is able to provide record-setting output power density at mmW frequencies with excellent power-added-efficiency and linearity. Measured transistor values show excellent potential for both power and low noise amplification applications. With I DS >2.4A/mm, f T =50GHz, f max =100GHz, we are able to demonstrate Pout= 9.5W/mm, PAE = 41 %, and OIP3/P1dB =14dB at 30GHz.

The Super-Lattice Power Amplifier with Diamond Enhanced Superjunction (SPADES) device is being developed to enable a 2x increase in breakdown voltage of a Super-Lattice Castellated Field Effect Transistor (SLCFET) device. Incorporation of a diamond superjunction (SJ) within the drain region of a SLCFET was previously predicted to improve breakdown voltage with minimal impact on performance. P-type doped nanocrystalline diamond (NCD) is grown within etched trenches in the drain region of a SLCFET and tied to the gate, forming an active vertical field plate to laterally distribute electric field. Under high drain bias, mutual depletion regions are formed in the current carrying ridges and NCD in the drain region. This results in lower parasitic capacitance compared to a metal field plate, an important consideration for millimeter wave applications. On devices with an NCD SJ, we observe minimal capacitance penalty, low dispersion, and breakdown voltage behavior consistent with TCAD model prediction.

Heat extraction from novel GaN/AIGaN superlattice castellated field effect transistors developed as an RF switch is studied. The device thermal resistance was determined as 19.1 +/- 0.7 KAW/mm) from a combination of Raman thermography measurements, and gate resistance thermometry. Finite element simulations were used to predict the peak temperatures and show that the three-dimensional gate structure aids the extraction of heat generated in the channel. The calculated heat flux in the castellations shows that the gate metal provides a high thermal conductivity path, bypassing the lower thermal conductivity superlattice, reducing channel temperatures by as much as 23%.

This report describes the second generation (Gen2) of the Superlattice Castellated Field Effect Transistor (SLCFET) amplifier. The SLCFET amplifier is a new device that uses 3-dimensional device geometry to modulate a superlattice of multiple AlGaN/GaN channels. The superlattice enables extremely low source and drain resistances and high output current and power density, while the 3-dimensional, low-resistance T-gate provides good electrostatic control and high gain. The wide bandgap material system also provides a high breakdown voltage. These properties lead to a robust, high performance device for low-noise and power amplifier applications. Process improvements allow the Gen2 device to reach FT/FMAX of 76/130 GHz. At 10 GHz, noise characterization achieves a minimum NFmin of 0.699 dB and load pull measurements achieve over 70% peak Power Added Efficiency (PAE).

We report on the super-lattice castellated field-effect transistor (SLCFET) device architecture whose unique geometry enables new scaling and optimization strategies for RF power and performance. Measured transistor values show excellent potential for both power and low-noise amplification applications. With I-DS > 1.8 A/mm, f(T) = 47GHz, and f(max) = 124GHz, we are able to demonstrate P-out > 6 W/mm, PAE > 45%, and OIP3/PDC = 6 dB at 30 GHz.

The Minimum Airflow Particle Counter (MAPC) is a portable, low-power, low-cost, wireless optical counter which has been specifically designed for ultra-low-maintenance operation in heavily polluted environments. When exposed continuously to air with high particulate matter concentrations, the primary mode of failure for particle counters is a build-up of dust within the instrument. The MAPC circumvents this failure mode by severely restricting airflow through the system, enabling an estimated 5-year maintenance cycle. Such a long operational lifetime makes this instrument particularly suitable for IOT applications such as environmental air quality monitoring and pollutant source attribution using spatially distributed wireless sensor networks. Here, we present the theory of operation, instrument design, and collected data from a two-month field deployment in Beijing. We find that the MAPC performs comparably to other low-cost optical counters, but with a significantly enhanced maintenance-free operational lifetime.

The LER and LWR of subtractively patterned Si and SiN waveguides was calculated after each step in the process. It was found for Si waveguides that adjusting the ratio of CF4: CHF3 during the hard mask open step produced reductions in LER of 26 and 43% from the initial lithography for isolated waveguides patterned with partial and full etches, respectively. However for final LER values of 3.0 and 2.5 nm on fully etched Si waveguides, the corresponding optical loss measurements were indistinguishable. For SiN waveguides, introduction of C4H9F to the conventional CF4/CHF3 measurement was able to reduce the mask height budget by a factor of 5, while reducing LER from the initial lithography by 26%.