This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the nonpersistent cross section causes a temporary interruption of service. These cross sections have been measured for several designs using fault-injection and proton testing. Some FPGA applications may realize increased reliability at lower costs by focusing SEU mitigation on just the persistent cross section.

This paper provides a methodology for estimating the proton and heavy ion static saturation cross-sections for multi-bit upsets (MBUs) in Xilinx field-programmable gate arrays and describes a methodology for determining MBUs' effects on triple-modular redundancy protected circuits. Experimental results are provided.

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based FPGAs make them very interesting for high-speed, on-orbit data processing, but, because the current generation of radiation-tolerant SRAM-based FPGAs are derived directly from COTS versions of the chips, several issues must be dealt with for space, including SEU sensitivities, power consumption, thermal problems, and support logic. This paper will discuss Los Alamos National Laboratory's approach to using the Xilinx XQVR1000 FPGAs for on-orbit processing in the Cibola Flight Experiment (CFE) as well as the possibilities and challenges of using newer, system-on-a-reprogrammable-chip FPGAs, such as Virtex I1 Pro, in space-based reconfigurable computing. The reconfigurable computing payload for CFE includes three processing boards, each having three radiation-tolerant Xilinx XQVRl 000 FPGAs. The reconfigurable computing architecture for this project is intended for in-flight, real-time processing of two radio fi-equency channels, each producing 12-bit samples at 100 million samples/second. In this system, SEU disruptions in data path operations can be tolerated while disruptions in the control path are much less tolerable. With this system in mind, LANL has developed an SEU management scheme with strategies for handling upsets in all of the FPGA resources known to be sensitive to radiation-induced SEUs. While mitigation schemes for many resources will be discussed, the paper will concentrate on SEU management strategies and tools developed at LANL for the configuration bitstream and 'half latches'. To understand the behavior of specific designs under SEUs in the configuration bitstream, LANL and Brigham Young University have developed an SEU simulator using ISI's SLAACl-V reconfigurable computing board. The simulator can inject single-bit upsets into a design's configuration bitstream to simulate SEUs and observe how these simulated SEUs affect the design's operation. Using fast partial configuration, the simulator can cover the entire bitstream of a Xilinx XQVRl 000 FPGA, which has 6 million configuration bits, in about 30 minutes. Instead of using a combination of TMR and configuration scrubbing for bitstream SEU mitigation, the approach developed for CFE uses minimal logic redundancy along with an SEU detection and correction scheme to handle bitstream SEUs. Though this approach allows some SEUs to affect less critical user logic, it requires considerably fewer FPGA resources than TMR and allows bitstream SEU rates to be monitored. 'Half latches', another class of SEU sensitive FPGA state elements, are used to provide logic constants in user FPGA designs but are not explicitly controlled by the configuration bitstream. Upsets in half latches cannot be detected by readback nor corrected via configuration repair or scrubbing - only a full reconfiguration can reliably restore their state. We have created a tool, called RadDRC, which can replace all critical half latches with more visible and correctable constant sources. Lastly, in looking forward, this paper will briefly consider the possible benefits and risks of using reconfigurable system-on-a-chip FPGAs, such as the Virtex II Pro, for reconfigurable computing in space. The paper concludes with a summary of challenges for using reconfigurable computing in space and a summary of future research at LANL in this area.

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field programmable gate arrays (FPGAs) make them very interesting for high-speed on-orbit data processing, but the current generation of radiation-tolerant SRAM-based FPGAs are based on commercial-off-the-shelf technologies and, consequently, are susceptible to single-event upset effects. In this paper, we d...

An accelerator test was used to validate the performance of an FPGA single event upset (SEU) simulator. The Crocker Nuclear Laboratory cyclotron proton accelerator was used to irradiate the SLAAC1-V, a Xilinx-Virtex FPGA board. We also used the SLAAC1-V as the platform for a configuration bitstream SEU simulator. The simulator was used to probe the "sensitive bits" in various logic designs. The objective of the accelerator experiment was to characterize the simulator's ability to predict the behavior of a test design in the pro ton beam during a dynamic test. The test utilized protons at 63.3 MeV, well above the saturation cross-section for the Virtex part. Protons were chosen because, due to their lower interaction rate, we can achieve the desired upset rate of about one configuration bitstream upset per second. The design output errors and configuration upsets Were recorded during the experiment and compared to results from the simulator. In summary, for an extensively tested design, the simulator predicted 97 % of the output errors observed during radiation testing. The SEU simulator can now be used with confidence to quickly and affordably examine logic designs to 'map' sensitive bits, to provide assurance that incorporated mitigation techniques perform correctly, and to evaluate the costs and benefits of various mitigation strategies. The simulator provides an excellent test environment that accurately represents radiation induced configuration bitstream upsets.

Compute performance and algorithm design are key problems of image processing and scientific computing in general. For example, imaging spectrometers are capable of producing data in hundreds of spectral bands with millions of pixels. These data sets show great promise for remote sensing applications, but require new and computationally intensive processing. The goal of the Deployable Adaptive Processing Systems (DAPS) project at Los Alamos National Laboratory is to develop advanced processing hardware and algorithms for high-bandwidth sensor applications. The project has produced electronics for processing multi- and hyper-spectral sensor data, as well as LIDAR data, while employing processing elements using a variety of technologies. The project team is currently working on reconfigurable computing technology and advanced feature extraction techniques, with an emphasis on their application to image and RF signal processing. This paper presents reconfigurable computing technology and advanced feature extraction algorithm work and their application to multi- and hyperspectral image processing. Related projects on genetic algorithms as applied to image processing will be introduced, as will the collaboration between the DAPS project and the DARPA Adaptive Computing Systems program. Further details are presented in other talks during this conference and in other conferences taking place during this symposium.

It is not uncommon for remote sensing systems to produce in excess of 100 Mbytes/sec. Los Alamos National Laboratory designed a reconfigurable computer to tackle the signal and image processing challenges of high bandwidth sensors. Reconfigurable computing, based on field programmable gate arrays, offers ten to one hundred times the performance of traditional microprocessors for certain algorithms. This paper discusses the architecture of the computer and the source of performance gains, as well as an example application. The calculation of multiple matched filters applied to multispectral imagery, showing a performance advantage of forty- five over Pentium II (450 MHz), is presented as an exemplar of algorithms appropriate for this technology.

Rf signals are dispersed in frequency as they propagate through the ionosphere. For wide-band signals, this results in nonlinearly-chirped-frequency, transient signals in the VHF portion of the spectrum. This ionospheric dispersion provides a means of discriminating wide-band transients from other signals (e.g., continuous-wave carriers, burst communications, chirped- radar signals, etc.). The transient nature of these dispersed signals makes them candidates for wavelet feature selection. Rather than choosing a wavelet ad hoc, we adaptively compute an optimal mother wavelet via a neural network. Gaussian weighted, linear frequency modulate (GLFM) wavelets are linearly combined by the network to generate our application specific mother wavelet, which is optimized for its capacity to select features that discriminate between the dispersed signals and clutter (e.g., multiple continuous-wave carriers), not for its ability to represent the dispersed signal. The resulting mother wavelet is then used to extract features for a neural network classifier. The performance of the adaptive wavelet classifier is then compared to an FFT based neural network classifier.

FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-earth orbit, FPGAs are susceptible to Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artifically upsets the configuration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This simulation tool is being used to characterize the reliability of SEU mitigation techniques for FPGAs.