The DAMIC-M (DArk Matter In CCDs at Modane) experiment employs thick, fully depleted silicon charged-coupled devices (CCDs) to search for dark matter particles with a target exposure of 1 kg-year. A novel skipper readout implemented in the CCDs provides single electron resolution through multiple non-destructive measurements of the individual pixel charge, pushing the detection threshold to the eV-scale. DAMIC-M will advance by several orders of magnitude the exploration of the dark matter particle hypothesis, in particular of candidates pertaining to the so-called "hidden sector." A prototype, the Low Background Chamber (LBC), with 20g of low background Skipper CCDs, has been recently installed at Laboratoire Souterrain de Modane and is currently taking data. We will report the status of the DAMIC-M experiment and first results obtained with LBC commissioning data.

The DArk Matter In CCDs at Modane (DAMIC-M) experiment is designed to search for light dark matter ( m(X) < 10 GeV/c(2)) at the Laboratoire Souter rain de Modane (LSM) in France. DAMIC-M will use skipper charge-coupled devices (CCDs) as a kg-scale active detector target. Its single-electron resolution will enable eV-scale energy thresholds and thus world-leading sensitivity to a range of hidden sector dark matter candidates. A DAMIC-M prototype, the Low Background Chamber (LBC), has been taking data at LSM since 2022. The LBC provides a low-background environment, which has been used to characterize skipper CCDs, study dark current, and measure radiopurity of materials planned for DAMIC-M. It also allows testing of various subsystems like readout electronics, data acquisition software, and slow control. This paper describes the technical design and performance of the LBC.

For several years, a group of engineers and physicists from LAL and LPNHE have been working on the design of two front end ASICs dedicated to Charge Couple Devices (CCD). ASPIC (Analogue Signal Processing Integrated Circuit), designed in AMS CMOS 0.35 mu m 5V technology, is meant to readout and process the analog signals of CCDs. CABAC ( Clocks And Biases ASIC for CCDs), designed in AMS CMOS 0.35 mu m 50V technology, produces the clocks and biases needed by the CCDs to work at their full potential. This paper presents the performances of the final versions of these two ASICs.

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.

A new prototyped version of the SiTR_130 chip has b een achieved end of 2008 to process the signal from 88 strips and was tested in 2009. The g oal of this work is to pursue developing this Front-End and Readout chip for the Silicon strips a t the ILC able to equip larger size Silicon prototype than those currently built for the EUDET project. The goal is to achieve the handling of at least 128 channels and improve furth er e digital treatment of the information with implementing full programmability, flexibility , fault-tolerance for use in a large scale beam test infrastructure. A new version is being de signed for 2010, able to treat 128 channels. This Memo is also a NIMA article published for the TIPP09 Proceedings. EUDET-MEMO-2009-21 2

A 130nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low noise charge amplifier and integration with long pulse shaping, (ii) an eight by eight positions analog sampler for both storing successive events and reconstructing the full pulse shape, and (iii) a sparsifier performing analog sum of three adjacent inputs to decide whether there is signal or not. The whole system is controlled by the digital part, which allows configuring all the reference currents and voltages, drives the control signals to the analog memories, records the timing and channel information and subsequently performs the conversion to digital values of samples. The total surface of the circuit is 10×5mm2, with each analog channel occupying an area of 105×3500μm2, and the remaining space of about 9000×700μm2 being filled by the analog channels on the silicon.

We present a summary of last year activities within the JRA2 SiTRA subtask. Progress on front-end electronics, sensors R&D including very preliminary results from 2009 SPS test beams are brie∞y reported here.

Final results on a CMOS 0.18 µm front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 µm is briefly presented.

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.

This paper briefly describes the main R&D objectives that are undertaken within the international R&D collaboration SiLC aiming to build the next generation of silicon tracking devices especially in the case of the ILC. Firstly, motivation to use silicon detectors in the tracker is explained. Then basic aspects of the design and solutions proposed are described (sensors, front-end electronics, mechanics, alignment). First results from the lab and beam test of the front-end chips and module prototypes built are shown.

A 130nm CMOS evaluation chip intended to read Silicon strip detectors has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of a full signal processing chain, including low-noise charge integration and pulse shaping, a 16 deep-analog sampler triggered on an analogue sum of adjacent inputs, and a parallel 10-bit analog to digital conversion. Laboratory and in-situ tests results of the chip are reported, demonstrating the behavior and performance of the full sampling process and analog to digital conversion, on a laboratory test stand, and from radioactive source as well as beam tests. Each channel occupies an area of 100 x 600 square microns on Silicon, and dissipates less than half a milliwatt of static power.

For the years to come, Silicon strips detectors will be read using the smallest available integrated technologies for room, transparency, and power considerations. CMOS, Bipolar-CMOS and Silicon-Germanium are presently offered in deepsubmicron (250 down to 90nm) at affordable cost through worldwide integrated circuits multiproject centers. As an example, a 180nm CMOS readout prototype chip has been designed and tested, and gave satisfactory results in terms of noise and power. Beam tests are under work, and prospectives in 130nm will be presented.

A highly integrated readout scheme for silicon trackers making use of deep sub-micron CMOS electronics (DSM) is presented. In the context of the International Linear Collider (ILC) trackers developments, a 16-channel readout chip for silicon strips detector has been designed in 180 nm CMOS technology, each channel comprising a low noise amplifier, a pulse shaper, a sample and hold and a comparator. Results are presented.