Modern embedded systems such as autonomous vehicles and robotics increasingly rely on high-performance computing to satisfy real-time and data-intensive demands. Parallel code generation, which combines task- and data-parallelism, is essential to efficiently utilize heterogeneous platforms composed of CPUs and accelerators. This study proposes a model-based code-generation workflow that integrates Halide, a domain-specific language (DSL) for performance-optimized library generation, into a model-based parallelization framework. The proposed approach addresses the challenge of jointly optimizing task mapping, scheduling, and data partitioning in heterogeneous systems. For data- parallel tasks, we propose two integer linear programming (ILP) formulations: a function-based method assuming a function model of execution time and an interpolation-based method using sampled profiling data. This enables precise load balancing across the CPUs and accelerators. We performed experiments on random task graphs and practical Simulink models executed on both a PC and Jetson Orin Nano. Compared to the C code generated from Embedded Coder, our methods achieve over 650x on a PC and 50x on Jetson. The proposed ILP formulations outperformed other traditional task mapping and scheduling strategies. We also executed the tool under different heterogeneous computing APIs, including CUDA, OpenCL , and Vulkan, and conducted parallel performance tests to demonstrate its potential for portability.

This paper presents a templated approach for automatic generation of optimized library functions using Halide as a replacement for the functions generated by Simulink. Although Simulink is widely used for the development of embedded systems, the automatically generated code may have limitations in compute-intensive models. Therefore, we propose library function generation using Halide from prewritten templates, extracting the Simulink model parameters using a model-based parallelizer. Experiments were conducted on central processing units (CPUs) and graphical processing units (GPUs) to evaluate performance. On CPUs, compared with compiler vectorization and the basic linear algebra subprograms (BLAS) library, Halide achieved up to 65.77 times speedup in multi-core and up to 36.20 times speedup in single-core scenarios. Although Halide did not always outperform BLAS for larger matrix sizes, it still showed considerable improvements. On GPUs, experiments on MX450 and Jetson platforms demonstrated that Halide’s performance was comparable to that of cuBLAS and even surpassed it for larger matrices.

Integrated systems comprise diverse tasks, including real-time control and image processing, which must be efficiently executed on embedded system-on-chips with high performance and low power consumption. Multi-core and heterogeneous central processing unit (CPU) architectures, such as Intel’s performance-efficient X86 CPUs, can optimize task execution. Model-based development tools, such as MATLAB/Simulink have further streamlined software design, enabling automatic code generation for embedded systems. This study addresses the challenges of task mapping and scheduling in model-based parallelization (MBP) by focusing on bottleneck tasks that exhibit data parallelism. Control systems may have several dependencies that cause numerous sequential parts and idle times, particularly when the cores exhibit varying performances. Existing methods that rely on even data partitioning may result in suboptimal performance. We propose an ILP task mapping and scheduling framework that introduces uneven data partitioning and optimizes workload balance by filling idle times. Additionally, we present an enhanced MBP workflow that utilizes OpenCV libraries and generates a general pthread code, which improves compatibility across platforms. For random task graphs, the improvement in parallel speedup is approximately 10.02%. For three Simulink models, including a real-world model on single-ISA heterogeneous CPUs, the improvements are 26.25%, 26.55%, and 19.83%.

This paper presents a templated approach to automatically generate a library function to replace a function generated in Simulink. Simulink is used in model-based development and is known for generating optimized code for embedded systems through methods such as expression folding and variable reuse. However, for compute-intensive models, the efficiency of the generated code may be limited. To address this issue, integrating calls to external libraries into Simulink’s code is common. Consequently, the choice and performance of these libraries significantly affect the overall efficiency. Halide has proven effective for authoring high-performance compute-intensive code. It boasts an efficient automatic scheduling tool that generates optimized code tailored to different platforms and adjusts adaptively for various input scales. In this paper, we propose a library function generation with Halide from pre-written templates and Simulink model parameters extracted by Model-Based Parallelizer (MBP). Experimental results show a maximum 80 times speed-up for compute-intensive functions.

In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data- and task-parallelism is crucial during this process. For data parallelism, a RISC-V Simulink library written in vector codes is prepared for blocks with sufficient vector or matrix calculations. Moreover, large inputs can be divided, which means that tasks can be executed simultaneously using multiple cores. For task parallelism, integer linear programming (ILP) is designed to deploy tasks on scalar processing elements (SPEs) and a vector processing element (VPE) of MIMDV. The use of a vector library for a task and the number of SPEs a task uses are determined. To reduce the overhead, synchronization is realized by barrier wait, and execution is divided into multiple time intervals called layer. We propose a novel one-step ILP that accurately minimizes the parallel time of such a situation. Furthermore, we propose a two-step ILP to achieve reasonable performance in practical time. One step is SPE mapping, and the other is layer scheduling. We tested our methods using random task graphs and real-world applications on DR1000C, a type of RISC-V MIMD processor with a vector accelerator.

The three-dimensional (3D) normal distributions transform (NDT) is a popular scan registration method for 3D point cloud datasets. It has been widely used in sensor-based localization and mapping applications. However, the NDT cannot entirely utilize the computing power of modern many-core processors, such as graphics processing units (GPUs), because of the NDT’s linear nature. In this study, we investigated the use of NVIDIA’s GPUs and their programming platform called compute unified device architecture (CUDA) to accelerate the NDT algorithm. We proposed a design and implementation of our GPU-accelerated 3D NDT (GPU NDT). Our methods can achieve a speedup rate of up to 34 times, compared with the NDT implemented in the point cloud library (PCL).

This study presents a method for estimating the latency of each LLVM-IR instruction to enable effective parallelization in model-based development. In recent embedded systems, such as in-vehicle electronic control, multi-many-core processors are utilized for the hardware, and model-based development for software. In the design of these systems, the degree of parallelism in the software and accuracy of performance estimation in the early design stages of the model-based development can be improved by estimating the performance of the blocks in the models and utilizing the estimate for parallelization. Research is therefore being performed on a software performance estimation technique that uses IEEE2804-2019 hardware feature description called Software-Hardware Interface for Multi-many-core (SHIM). In SHIM, each LLVM-IR instruction is associated with an execution cycle of the target processor. Several types of assembly instruction sequences are generated for the target processor from a given LLVM-IR instruction; thus, it is not easy to estimate the number of execution cycles. In this study, we propose a method that uses deep neural networks to estimate execution cycles for each LLVM-IR instruction. It can be observed that our method obtains a better estimation of LLVM-IR instruction latency compared with previous methods in experiments using the Raspberry Pi3 Model B+.

Multi/many-core processors are being increasingly used to reduce power consumption and improve performance. The use of model-based development for embedded systems has also been increasing. Relative to these trends, the model-based parallelizer or MBP has an essential role in parallelizing applications at the model level. MBP maps Simulink blocks to cores using various types of information such as block characteristics, C code, and multi/many-core hardware implementation. However, MBP does not consider many-core hardware with cluster structures such as Kalray MPPA2-256 processor which contains 16 clusters of 16 cores for 256 general-purpose cores in total. This paper proposes an algorithm that determines core allocations by considering cluster structures. The proposed algorithm combines two other algorithms: one algorithm uses the core allocation of MBP and path analysis at the cluster-level and considers effects from communication contention when determining cluster allocations, and the other algorithm uses the results from MBP and remaps cluster allocations. The proposed algorithm produces better results than its component algorithms could produce separately. Evaluations demonstrate that the proposed algorithm obtained the best results among four methods in terms of execution time on Simulink models.

ABSTRACT: Ego-vehicle localization is a critical technology in autonomous driving systems, and one of the widely used methods for localization is scan matching between a 3D map and real-time LiDAR scan. This method is known to fail due to factors such as an incorrect initial position and orientation for scan matching. In this paper, we propose a simulator-based localization evaluation framework to verify the robustness of localization. By using a simulator, localization can be evaluated without driving a real vehicle, and can be evaluated by creating disturbances such as traffic jams. Our framework also allows to evaluate the robustness of localization by using multiple particles with random errors of the initial position and orientation for scan matching to simulate dead reckoning errors caused by multiple factors such as road surface conditions and tire diameter. In the evaluation experiments, we confirmed that the robustness of localization can be evaluated by applying this method to factors such as sensor setup, disturbances in the traffic environment, and the amount of 3D features in the environment.

The increasing scale and complexity of embedded systems and the use of multi-many-core processors have resulted in a corresponding increase in the demand for software development with a high degree of parallelism. The degree of parallelism in software and the accuracy of performance estimation in the early design stages of model-based development can be improved by estimating performance of blocks in models and utilizing the estimate for parallelization. Research is therefore being performed on a software performance estimation technique that uses the IEEE2804-2019 hardware feature description called software-hardware interface for multi-many-core (SHIM). In SHIM, each LLVM-IR instruction is associated with the execution cycle of the target processor. Because several types of assembly instruction sequences for the target processor are generated from a given LLVM-IR instruction, it is not easy to estimate the number of execution cycles. In this study, we propose a regression analysis method to estimate the execution cycles for each LLVM-IR instruction. It is observed that our method estimated the execution cycles within the target error of ±20% in experiments using a Raspberry Pi3 Model B+.

In this paper, we present a first-of-its-kind method to determine clear and repeatable guidelines for single-shot camera intrinsic calibration using multiple checkerboards. With the help of a simulator, we found the position and rotation intervals that allow optimal corner detector performance. With these intervals defined, we generated thousands of multiple checkerboard poses and evaluated them using ground truth values, in order to obtain configurations that lead to accurate camera intrinsic parameters. We used these results to define guidelines to create multiple checkerboard setups. We tested and verified the robustness of the guidelines in the simulator, and additionally in the real world with cameras with different focal lengths and distortion profiles, which help generalize our findings. Finally, we used a 3D LiDAR (Light Detection and Ranging) to project and confirm the quality of the intrinsic parameters projection. We found it possible to obtain accurate intrinsic parameters for 3D applications, with at least seven checkerboard setups in a single image that follow our positioning guidelines.

This paper presents a parallelization workflow in model-based development for a MIMD (Multiple Instruction streams, Multiple Data streams) processor with a vector accelerator. In the workflow, an Integer Linear Programming (ILP) formulation is proposed to deploy tasks extracted from the Simulink model. The proposed formulation can determine the number of processors that a task needs, and whether vectorization should be used to accelerate a task to reduce synchronization overhead and execution time. In the experiments, a MATLAB script was used to simulate the ILP formulation with randomly generated task graphs and evaluate its performance. Furthermore, we applied ILP task mapping to a real-world Model Predictive Control (MPC) application on DR1000C, a type of RISC-V MIMD processor with a vector accelerator. The maximum speedup of 10. 05x is obtained, which is promising for use in real-time embedded systems.

According to the increase in the required performance of the product, a multi-core processor that can process tasks simultaneously is attracting attention. To efficiently utilize a multi-core processor, a Model-Based Parallelization Tool(MBP) technology has been proposed to automatically generate paral-lelization code in consideration of the causal relationship of the control system. However, parallel processing time and control performance verification in real systems have not been sufficiently investigated. In this paper, to verify the validity of the parallelization code automatically generated by the MBP on a real system, we compare and review the single-code of the function unit by hand and the parallel code automatically generated by the MBP. In addition, we verify the MBP Tool by analyzing parallelization results as well as points to consider when implementing a motor control system.

In this paper, we propose a method to automatically generate parallelized code from Simulink models, while exploiting both task and data parallelism. Building on previous research, we propose a model-based parallelizer (MBP) that exploits task parallelism and assigns tasks to CPU cores using a hierarchical clustering method. We also propose amethod in which data-parallel SYCL code is generated from Simulink models; computations with data parallelism are expressed in the form of S-Function Builder blocks and are executed in a heterogeneous computing environment. Most parts of the procedure can be automated with scripts, and the two methods can be applied together. In the evaluation, the data-parallel programs generated using our proposed method achieved a maximum speedup of approximately 547 times, compared to sequential programs, without observable differences in the computed results. In addition, the programs generated while exploiting both task and data parallelism were confirmed to have achieved better performance than those exploiting either one of the two.

The perception of the surrounding circumstances is an essential task for fully autonomous driving systems, but its high computational and network loads typically impede a single host machine from taking charge of the systems. Decentralized processing is a candidate to decrease such loads; however, it has not been clear that this approach fulfills the requirements of onboard systems, including low latency and low power consumption. Embedded oriented graphics processing units (GPUs) are attracting great interest because they provide massively parallel computation capacity with lower power consumption compared to traditional GPUs. This study explored the effects of decentralized processing on autonomous driving using embedded oriented GPUs as decentralized units. We implemented a prototype system that off-loaded image-based object detection tasks onto embedded oriented GPUs to clarify the effects of decentralized processing. The results of experimental evaluation demonstrated that decentralized processing and network quantization achieved approximately 27 ms delay between the feeding of an image and the arrival of detection results to the host as well as approximately 7 W power consumption on each GPU and network load degradation in orders of magnitude. Judging from these results, we concluded that decentralized processing could be a promising approach to decrease processing latency, network load, and power consumption toward the deployment of autonomous driving systems.

In recent years, there has been a demand for deep neural network (DNN) inference applications in embedded systems. We are developing a framework to design hardware (HW) on an FPGA for DNN inference. Although low-end FPGAs are needed to reduce the cost, FPGAs have limited internal memory (Block RAM, BRAM). Therefore, it is necessary to use SDRAM instead of BRAM, but to speed up the access to SDRAM, a prefetcher is needed that can be used in the system-level design. In this study, we designed a prefetch architecture in a systemlevel design environment that can be easily implemented in C code for high-level synthesis. We propose a method of storing data in the BRAM by transferring the data in a burst. We designed DNN inference HW with external memory (SDRAM) access using prefetch architecture. As a result, the prefetch design is faster than cases using BRAM or SDRAM. In particular, it is found that the performance is up to a factor of 10 faster than that of SDRAM access without prefetch.

Collaborative filtering (CF) is a technique used in recommender systems to provide meaningful suggestions based on known feedback obtained from like-minded users. The measure of similarity plays a critical role in the performance of neighborhood-based CF methods. However, conventional similarity measures suffer from limitations because they only consider the direction of the rating vectors. We propose a novel similarity measure that considers the semantic nuances of the ratings; in particular, it weights the contributions of ratings in proportion to the users' degree of indifference towards the items. Additionally, to address the sparsity problem that affects the performance of CF techniques, we propose a switching hybrid method that predicts user ratings based on either our custom similarity measure or through user and item biases. We evaluated the proposed method on six different datasets and compared it with other CF methods. The results show that the proposed recommender consistently outperforms those using conventional similarity measures when the sparsity of the dataset is high.

In this paper, we propose a model-based approach to parallelize Simulink models on multicore CPUs and NVIDIA GPUs at the block level and generate CUDA C codes for parallel execution. In our proposed approach, the Simulink models are converted to directed acyclic graphs (DAGs) based on their block diagrams, wherein the nodes represent tasks of grouped blocks in the model and the edges represent the communication behaviors between blocks. Next, a path analysis is conducted on the DAGs to extract all execution paths and calculate the length of each path, which comprises the execution times of tasks and the communication times of edges on the path. Then, an integer linear programming (ILP) formulation is used to minimize the length of the critical path of the DAG, which represents the execution time of the Simulink model. The ILP formulation also balances the workloads on each CPU core for optimized hardware utilization. We evaluate the proposed approach by parallelizing an image processing model on a platform of two homogeneous CPU cores and two GPUs to determine its effectiveness.

The scope of embedded systems used by multicore processors is widely applied to various products that require control, such as home appliances, industrial devices, transportation devices, and communication terminals. Model-Base Parallelization technology was proposed towards efficient parallelization to implement a control system in the introduction of multi-core processors. By applying MBP, it is possible to parallelization even details that people are not aware of, but the control system with numerous causal relationships still does not sufficiently utilize multi-core. Therefore, a method of inserting a time-delay is being studied as a method for improving the parallelization of multi-cores. In this paper, We describe the insertion location that improves parallelization and does not affect the control performance by inserting time-delay to implement the vector control system of PMSM on multi-core efficiently.