Memories with Error Correction Codes (ECC) are essential for high-safety and high-reliability applications. Ensuring the integrity of ECC logic requires thorough testing during both manufacturing and in-system operation. While scan patterns are effective for ECC testing in manufacturing, they are unsuitable for in-system tests. Additionally, the ECC deep XOR tree structure leads to lengthy scan test pattern generation time. Although standard Memory Built-In Self-Test (MBIST) techniques are employed in both manufacturing and in-system tests, they provide limited fault coverage for ECC logic. This paper proposes a novel method for comprehensive ECC functionality testing, leveraging enhanced MBIST patterns with integrated fault injection capabilities. This approach offers a significant advantage by requiring only minimal modifications to existing MBIST hardware, without altering the memory or ECC design. Experimental results demonstrate high fault coverage for both stuck-at and transition faults on par with scan patterns. The method offers flexible deployment, applicable either independently or in conjunction with scan patterns for manufacturing testing, and independently for in-system testing, thereby significantly enhancing the overall quality assurance of ECC logic.

This short paper summarizes recent work on three test standards. Firstly, an update on IEEE Std. 1687-2014, currently going through a refresh, followed by development updates on two new standards IEEE P1687.2 and IEEE P2929.

Modern systems-on-chip integrate numerous embedded test instruments accessible through an IEEE 1687 (IJTAG) network. These instruments often operate in asynchronous clock domains, requiring robust interfaces for reliable data exchange. While synchronizer-based interfaces are commonly used, they exhibit significant limitations at high IJTAG clock frequencies. Existing clock-gating and multiplexing solutions remain incompatible with clock mesh methodologies widely adopted in modern designs. This paper introduces a novel self-adapting asynchronous interface that automatically adjusts IJTAG instrument operations, such as memory BIST, to match IJTAG clock characteristics while maintaining full compatibility with clock mesh architectures. The technique also adapts to IJTAG control signal stretching and TCK duty cycle variations. Simulation results demonstrate reliable operation, enabling efficient instrument test access in advanced semiconductor processes.

Compute-in-Memory (CiM) devices have several attributes that make them of interest especially for accelerating artificial intelligence workloads and, at the same time, reduce power consumption. Both are critical aspects of edge computing. This paper summarizes a 3-topic special session held at the European Test Symposium 2026 on the topic of CiMs: (a) concerning the reliability of CiMs, (b) the testing of CiMs, and finally (c) on the security of CiMs.

A novel test method is proposed to test 3nm technology register files with large numbers of read and write ports. Due to the large number of bit lines and word lines present in a single cell, it is difficult to correctly test relevant combinations and trigger faulty behavior. In this paper we propose an effective test method to provide comprehensive coverage of coupling faults across all bit line (BL) and word line (WL) combinations with minimal test time impact. This new technique considers multiple potential aggressors, independent of the memory layout or configuration. The comprehensive test is generated automatically with a commercial tool implementing Built-In Self-Test (BIST) circuitry around the memory. The hardware area overhead is minimized by sharing the concurrent write address and data generation logic between multiple ports.

Today’s logic chips and System-on-Chips (SoCs) are ever-growing in size, complexity, and integration density. This drives a continuous need to develop novel and advanced ways to efficiently test such devices after manufacturing. High-bandwidth IJTAG over SSN (HB-IJTAG) is one such innovation that leverages the high-speed and parallel Streaming Scan Network (SSN) bus to concurrently access many local IEEE 1687 (IJTAG) networks.However, every time the high-bandwidth IJTAG access mode is activated, it must first be configured through the global IJTAG network. The initial configuration and subsequent reconfigurations constitute a substantial test time overhead due to the lower shift speed and serial nature of global IJTAG.This paper introduces wide-ranging enhancements to the high-bandwidth IJTAG access to allow for persistent utilization of the high-speed SSN bus. By eliminating the reasons for the expensive reconfigurations, high-bandwidth IJTAG can remain active throughout the entire test session. This results in a significant reduction of test setup time and more efficient test delivery. Our experiments clearly demonstrate these benefits in different pattern delivery scenarios. Persistently using the high-bandwidth data delivery reduced the relevant IJTAG pattern execution time by up to 243x, yielding an up to 18x lower overall test time for SSN ATPG patterns.

The increasing complexity of Integrated Circuits (ICs) is driven by heterogeneous functionality and stringent performance demands. This necessitates scalable and efficient design for testability (DFT) solutions to ensure cost-effective test access and functional correctness. Streaming Scan Network (SSN) and High-Bandwidth IJTAG over SSN (HB-IJTAG) enhance the test efficiency significantly by accelerating the data transfer and optimizing the test execution. However, these technologies introduce validation challenges due to more intricate control mechanisms and their large-scale deployment.This paper presents a novel, holistic approach for generating and sequencing functional validation patterns. These patterns systematically leverage SSN and HB-IJTAG capabilities to optimize overall efficiency. The proposed methodology enables the concurrent and robust validation of hundreds of SSN and HB-IJTAG DFT components, significantly improving the overall test execution time.

Computation-in-Memory (CIM) has emerged as a promising solution to the memory bottleneck in data-intensive applications and AI accelerators; however, it introduces new testing challenges due to multi-row access patterns and higher sensitivity to variations. These challenges can cause marginal bitcells to fail under CIM operation even if they pass standard March tests, making existing approaches insufficient for ensuring reliable CIM operation. In this work, we propose March-CIM, a modified March test optimized for SRAM-based CIM, which overcomes this limitation. By using read current profiling and a trim-assisted sensing mechanism, our method identifies marginal bitcells that conventional tests miss and selectively subjects them to exhaustive CIM testing to verify their fault-free functionality. This method significantly reduces test time (and thus test cost) by eliminating unnecessary tests for the bitcells with reliable performance. We demonstrate the effectiveness of our CIM test approach using 22 nm FDSOI technology and confirm its compatibility with industrial memory built-in self-test (MBIST) tools with minor modifications, achieving a reduction of up to 67% in test time compared to exhaustive CIM testing. Our method is applicable for field testing to ensure reliable operation through periodically profiling bitcell behavior through MBIST under real-time infield conditions.

Computation in memory (CIM) is a promising solution to meet the increasing demand for fast and energy-efficient computations in applications such as neural network accelerators. Different memory technologies have been evaluated for CIM application, SRAM being one of the most viable ones due to its reliable properties based on many years of high-volume CMOS production. CIM requires simultaneous activation of multiple rows of SRAM to perform an arithmetic computation, in which the result is read out from a sensing circuit. In the presence of process variation, sensing circuitry is vulnerable to transistors and bitlines mismatch, causing faulty CIM results. In this paper, we propose an MBIST-compatible method to mitigate the sense amplifier mismatch in the post-manufacturing process during the memory test. This method utilizes MBIST to compensate for read circuitry mismatch by activating an extra set of bitcells to balance the read current. Our approach improves the mismatch tolerance by up to 40% compared to the transistor upsizing solution, which increases the sensing circuit size to compensate for process variation. The proposed method achieves a 24.4% improvement in delay at the cost of less than 1% higher average dynamic power and 2.58% area overhead compared to the transistor upsizing solution. Due to its MBIST compatibility, the proposed method can also be used in the field to improve reliability by compensating for run-time degradation, like the aging effect.

Adherence to the ISO 26262 standard requires periodic testing of embedded memories in automobiles, which must be completed within short time windows during normal vehicle operation. This testing must preserve memory contents post-test and integrate test logic seamlessly with system functionality, all while minimizing disruption to vehicle performance. This paper proposes a Memory Built-In Self-Test (MBIST) architecture that addresses these challenges by using a series of short test bursts. The architecture dynamically adjusts the length of each burst based on available memory idle time, ensuring efficient testing without interfering with critical system functions. Additionally, the architecture minimizes hardware overhead by reusing existing resources and introduces a direct access interface for tighter integration with system logic, further enhancing test efficiency and reducing latency.

Error correction codes (ECC) are techniques for detecting and correcting errors. The adoption of ECC is increasingly prevalent, driven by its ability to manage random defects in emerging memory technologies and to mitigate soft errors. When testing memories with ECC, the memory builtin self-test (BIST) logic must account for ECC's presence to accurately report the status during both manufacturing and insystem test. This paper details the innovations to memory BIST logic and the testing sequences to validate memories integrated with ECC, including those with redundancy.

Specialized external testers and custom load-boards cannot be used for testing die-to-die interfaces in a multi-chip in a package product as there is no access to the TX/RX buffers. On the other hand, small bump pitch allows for wafer test via sacrificial pads using a small set of signals. In this paper we discuss different techniques that can be used to test complex PADs and analog PHY interfaces. We show how these PADs with no synthesis libraries can be modeled for an EDA tool to automatically insert the wrapper logic. We also discuss how many of these ideas may be used by the IEEE P3405 standard, which would standardize testing of these interconnects.

Die-to-die (D2D) interconnects facilitating inter-chiplet communication are expected to grow exponentially over the coming years as more functionality is packed into multi-die packages. These interconnects need to be tested thoroughly to weed out all the defects before the chip is shipped. Further, continued monitoring during mission mode to catch an error before it causes a catastrophic system failure seems to become a requirement. To enable these tests, proper DFT architecture needs to be designed with careful considerations for die wrapper register (DWR), clock forwarding from one chiplet to another chiplet and placement of the interconnect on the interface grid. In this paper we propose several methods that when used together can deliver more effective known-good-die (KGD) and known-good-stack (KGS) testing and improved diagnosis.

Scaling down the transistor size enables a cost-effective high-performing solution in modern semiconductor designs. However, the added complexity of process and extremely small critical three-dimensional spacing of the transistor structure make it more challenging to maintain precise variation control. Defects introduced here can lead to different intermittent behaviors, some of which might not appear as fails during traditional testing procedures but might manifest as a system failure in the field. The emergence of artificial intelligence chip design has introduced high demands for a massive number of multi-cores connected in parallel with a huge memory array size in a chip. This further increases the importance of identifying rare tail events through in-depth diagnosis in advanced nodes. Various sophisticated algorithms have been proposed to improve defect coverage. However, the addition of algorithms may increase test cost tremendously while providing limited benefits for specific fault types which may not happen. Therefore, selecting a smart combination of algorithms that provide enough coverage for the specific product application is essential for cost-effective testing. In this paper, we review the electrical properties of marginal defects inserted in an SRAM device to evaluate test escapes in the latest technology. We also present a new algorithm to improve test coverage efficiency. A commercially available memory BIST tool was used to load a DFT compatible algorithm and operation set for memory test. A commercially available analog simulation tool was used in combination with a novel defect simulation flow to evaluate digital and analog behavior of the device.

Testing magnetoresistive random access memory (MRAM) presents several challenges, particularly in scaled technology nodes. One major challenge is the increased interconnect resistance from the bitline and sourceline, which leads to issues like the near-far effect, where bitcells farther from the sensing circuit exhibit higher resistance. Additionally, the fabrication process can result in defects that may not be easily detectable using conventional testing methods. Another factor that makes the screening process more difficult is the presence of process variation. This paper proposes a memory-built-in self-test (MBIST) compatible method that compensates for the interconnect resistance effect using multi-level references and memory partitioning. In addition, the proposed method aims to find the location in the memory array that is less affected by process variation and use it to adjust the screening boundaries for the entire memory to detect defective bitcells more effectively. On average, the proposed method shows around 50% defect coverage improvement and 76% weak bitcell coverage improvement over its previous counterparts. The detected defects will be further evaluated for repair by ECC or other redundancy schemes to maximize product quality and yield.

As Systems-on-Chip (SOC) designs grow in complexity, so do the challenges associated with testing them. Some of the obstacles SOC designers face include limited I/O and scan channels, routing and timing closure issues, increasing manufacturing test and defect diagnosis time, and growing test data volume. Various design-for-test (DFT) techniques exist to handle complex SOC designs that have multiple cores. One new DFT implementation technique is the streaming scan network (SSN) high-bandwidth parallel data bus. SSN addresses many of the SOC challenges by providing an optimized packet-based scan data delivery system. It also dynamically optimizes test time by adjusting the data applied to each core. However, SSN is limited to delivering scan data; it cannot be used to deliver data to individual instruments in a physical block using the IEEE 1687 (IJTAG) network. This paper introduces a new high-bandwidth IJTAG DFT technology that leverages the existing high-speed parallel SSN bus to drive the serial IJTAG network. It describes the DFT implementation methodology, the impact to the backend in terms of timing and SDC, and how verification was done by Intel as they deployed it on multiple dielets in their next generation client CPU. Moreover, data on area overhead and the overall test cost savings achieved is presented.

As PDL has been developed to be syntactically compatible with TCL, it is possible to use an interpreter to enhance test routines with programming features, such as variables, flow control, etc.. Moreover, one of the big novelties of IEEE 1687 is the native support of interactive behaviour thanks to the PDL-1 instruction set. which allows data read from the target system to be returned to TCL Interpreter. However, it is not quite clear what “Interactive behaviour” actually means and how it gets from simulation to automatic test equipment. IEEE 1687 is a “descriptive” standard, so there is no provision or limitation on the way the test routines will be executed and if and how they will interact with the System Under Test.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

IEEE Std P3405 is a new standardization activity under the umbrella of TTTC's Test Technology Standardization Committee (TTSC). In 2023, a Study Group formulated a Project Authorization Request (PAR), which was approved and since December 1, 2023, the P3405 Working Group is active under elected chair Sreejit Chakravarty. This standardization activity focuses exclusively on the test and repair of chiplets' inter-die interconnects. In the PAR, the scope of the activity is described as follows. "Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair. The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers' (prepackaging), Packagers', and End Users' test and repair objectives." In this special session, a handful prominent members of the Working Group express their personal views on the outcome of the standardization work. The views expressed are from the authors alone and do not necessarily align with the view of the IEEE Std P3405 Working Group.

As technology scales down, the interconnect parasitic resistance more dominantly affects performance degradation and test escapes. The wire resistance increase is especially a great challenge in resistive-based non-volatile memories (NVM) such as magnetic random access memory (MRAM) and resistive RAM (ReRAM) because it can cause faulty reading of the data. The resistive-based NVMs perform the read operation by sensing the bitcell resistance relative to a reference value. Therefore, additive parasitic resistances along the read path, including the bitline (BL) and sourceline (SL) resistances, may cause incorrect read operation. The additive path resistance also makes defect screening harder. A defect screening method designed to detect faulty bitcells located near the sensing circuit may not effectively screen out a bitcell located far from the sensing circuit with the same defectivity level and lead to test escapes. Utilizing a multi-level reference, the proposed new testing scheme compensates for the additive line resistance effect and improves coverage for local defect screening. The detected fault will be further evaluated for correction by ECC or repaired to maximize field coverage. The proposed method is applicable to existing industrial memory built-in self-test (MBIST) solutions with minor modifications.