Executing scan tests at very-low voltage is a long-known industry best practice to screen resistive latent defects and contribute to enabling < 1 Defective Part Per Million (DPPM) performance for Automotive products. To be effective, it is necessary for these tests to run at near the intrinsic low voltage capability of the silicon. Slowing shift and capture clocks are best practices deployed to overcome Very-Low-Voltage (VLV) test timing limitations, but there are other challenges. This paper discusses two activities that enabled true VLV testing in a single digit FinFET technology. The first discusses a design implementation in the General-Purpose IO pads that supported correct signal level shifting at VLV and avoided action of low voltage detect circuitry during VLV testing. The second describes a series of design of experiments to characterize the test instrumentation at VLV conditions and optimize settings to robustly execute the tests at VLV conditions.
At-speed logic scan tests are an important tool to ensure desired quality in mobile chips. During initial test pattern bring-up, tests that exhibit an unexpectedly high Vmin pose a risk of over-testing and production yield loss. This is particularly problematic if the Vmin of the test is significantly higher than that of the functional system workloads. In such situations, the at-speed logic scan test is debugged to find and resolve the source of the high Vmin. This paper describes an example case study of Vmin debug, in which a series of experiments are performed to identify the root cause as individual test patterns that capture the responses of unconstrained paths. We propose pre-silicon and post-silicon methods to improve Vmin by preventing problematic patterns and reducing the debug effort during test bring-up. Our methods have been verified on ATE to effectively improve Vmin by 28.83mV to 39.33mV with 0% to 0.5% pattern count inflation.
As semiconductor technology advances, small delay defects (SDDs) have become a major concern in System-on-Chip (SoC) testing due to shrinking timing margins. Moreover, diagnosing SDDs is getting even more challenging due to their subtle impact on circuit timing and the existence of process variations. This paper presents an SDD diagnosis method integrating timing-aware fault simulation with injected delay selection and a mismatch-weighted (MW) score method to enhance diagnostic accuracy. Rather than relying on fixed delay values, the proposed method determines injected delays based on the slack of transition paths, generating multiple delay sizes to improve fault simulation resolution. The MW score calculation adjusts contributions of failures, enhancing defect ranking and mitigating process variation effects. Experimental results demonstrate that the proposed method significantly improves SDD localization and reduces the number of fault candidates, outperforming conventional approaches in both accuracy and efficiency.
Scan-Based Design-For-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITEfor design modifications. We show that LITEsignificantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions.
System Level Test (SLT) of compute products, such as processors, graphic cards, or AI accelerators, can stress critical components on the platform to their rated maximum performance and thermal envelopes. This at-speed test requires thermal management solutions compatible with the dense SLT environment, deployable at scale. Here we introduce the challenges of thermal management in SLT, parameters that affect thermal envelopes, using a case study of DDR memory. We present typical thermal management solutions used in a high-volume system test, their advantages and shortcomings, introduce liquid cooled solutions that can overcome them, and the functional benefits of using advanced liquid cooled DIMM solutions at scale in test factories.
As silicon photonic integrated circuits (PICs) increase in complexity, ensuring their reliability against manufacturing and operational variations necessitates robust Design-for-Test (DfT) strategies. We present an adaptable methodology for DfT insertion in large-scale PICs, centered on physics-informed hypergraph partitioning. Our approach uniquely leverages hypergraph-based weighting derived from process sensitivities (e.g. etch, doping) and operational drifts (e.g. thermal, injection), quantified using partial derivatives from foundry data or Transfer Matrix Method (TMM) simulations. This assigns actionable risk values to both devices (nodes) and interconnects (hyperedges). We employ k-way partitioning to achieve finer sub-network isolation and targeted test access, crucial for vulnerability localization in complex PICs like multi-level ring resonator networks or large MZI-based crossbars. Experiments performed on PIC designs demonstrate the application of the proposed risk coverage metric to vulnerability localization and test point insertion, achieved with quantifiable and moderate overhead.
Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.
Latch arrays are increasingly popular in designs due to lower area overhead and power consumption compared to the alternative SRAM solution. In this paper we will visit the new scan strategies used in latch array design, its implementation flow, and the benefits of these changes to latch array test coverage. Scan solution has the advantage of smaller area overhead compared to the BIST solution. In addition, it also provides failure analysis capability, which is not available in the traditional BIST solution. It is proven that this innovative approach could achieve 100% SAF and TDF coverage for latch array core.For the surrounding logic of latch array, including BIST wrapper, due to complexity of clock gating logic and decoding logic, different latch array reset schemes are tested and compared. High quality latch array test is achievable with the proposed new scan strategies for latch array.
A novel IC monitoring approach is proposed that uses deep learning to identify delayed events when non-robust tests are applied. A sensor captures events during the clock period, and the collected data are fed into the deep learning model. The deep learning model is trained with the collected data from manufacturing tests for delay defects. Experimental results with ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits, considering process variations, demonstrate the accuracy and scalability of the proposed method.
Modern semiconductor design heavily relies on the integration of IPs from 3PIP vendors to improve design efficiency and reduce time to market. However, such collaboration introduces security concerns, including unintentional bugs and opportunities for adversaries to insert hardware Trojans. Confidentiality verification is widely applied for detecting design weaknesses capable of leaking sensitive information through output ports of a chip or IP module. In this paper, we present QuEST, a novel confidentiality verification framework that identifies data leakage by analyzing statistical dependencies between multiple input and output ports. Moreover, QuEST augments traditional leakage detection techniques through Shannon entropy-based metrics, most notably mutual information and conditional mutual information, to quantify the extent of data leakage. This quantitative feature enables designers to systematically verify and assess security vulnerabilities more effectively that existing approaches. Experiments show that QuEST successfully detects data leakage caused by hardware Trojans in 11 Trust-hub benchmarks. In general, QuEST serves as a promising confidentiality analysis tool that enables designers to detect and quantify data leakage, thus bolstering the security posture of modern hardware designs.
Fan-out wafer-level packaging enables heterogeneous chiplet integration via Cu pillars and redistribution layers (RDLs). As FOWLP technology evolves, the focus is shifting towards many-chiplet designs, necessitating multi-layer RDL structures to route interconnects between these chiplets. However, defects such as opens, shorts, and coupling are a challenge for RDL structures. High-density, multi-layer RDLs exacerbate these challenges, leading to intensified coupling, elevated switching activity, and shorts within metal segments. Moreover, the finer pitch of RDLs increases electromigration due to rising current densities. We propose a routing-aware testing framework that leverages the multi-layer RDL routing Information to target realistic shorts and coupling defects. By physically partitioning interconnects into regions, we enable test scheduling and leverage shared test-pattern generators for launching test patterns and capturing responses to reduce test time and area overhead without compromising fault coverage. The framework’s effectiveness is demonstrated on four many-chiplet package designs with varying configurations of chiplet-to-chiplet connectivity. Our results show that this method can achieve over 99.8 % fault coverage with an n-fold reduction in test area and test time through an n-way partitioning strategy.
Microcontroller (MCU) performance screening ensures devices meet the maximum operating frequency Fmax specification. Speed Monitors (SMONs), implemented as ring oscillators, are used to estimate Fmax. Traditional machine learning (ML) models have been explored for this task but require extensive feature engineering and tuning. This work investigates Tabular Foundation Models, specifically TabPFN, for MCU performance prediction. TabPFN leverages in-context learning, enabling accurate inference without dataset-specific training. We evaluate its performance on a composite dataset combining four distinct MCU product families. Results show that TabPFN matches or exceeds baseline ML models while eliminating the need for manual optimization, offering a promising direction for efficient screening in semiconductor manufacturing with minimal human supervision
Chips with multiple interconnected dies in a package offer significant advantages over those with only a single monolithic die and this is driving the rapid adoption of multi-die packages in the market. In such packages, die-to-die interconnects are typically realized as large, dense arrays of fine-pitch micro-bumps or hybrid bonds, prone to manufacturing defects like shorts and opens. To address this, typically some spare interconnects are included to "repair" defective ones. This paper introduces an Interconnect Repair Language (IRL), based on Google’s Protocol Buffers, to describe all repair provisions. It also presents benefit/cost metrics for evaluation of a repair solution. As benefit metric, we use the spare and repair ratios, while costs are expressed as additional silicon area and propagation delay. We illustrate IRL and the various metrics with a running example from UCIe-Advanced 2.0. Finally, the paper presents a list of potential EDA tools based on the proposed IRL.
Reliability-demanding devices often require numerous fault injections (FIs) for reliability analysis in the product cycle. However, software-based FI typically demonstrates extremely low efficiency due to low simulation throughput, especially for large-scale designs, while hardware-based FI presents challenges related to complexity of setup and limited scalability. Additionally, FIs often occur in intervals where errors do not affect the system’s outcome, e.g., after final read before next write, necessitating efficient pruning of non-impactful FIs. To address this, a general-purpose FI-specialized framework, Genshin, is proposed for rapid reliability analysis. On the hardware side, we provide an FI-specialized design, which works with Design Under Test (DUT) chips on PCB boards and supports FI control based on the scan chain (SC). An integrated programmable logic allows for flexible and custom FI pattern definitions. Furthermore, an architecturally correct execution (ACE) analysis generates pruned fault tables for DUTs. In Genshin, the SC logic achieves 3,802-65,388 cycles/FI across SC lengths ranging from 2,795 to 61,393 in different DUTs, while the programmable logic enables custom error patterns such as layout-aware multi-bit upset (MBU). Furthermore, the pruned fault tables achieve fault reduction rates from 45.80% to 83.21%.
This paper discusses test techniques used to create an exceptionally reliable high-performance processor using an ultra-dense SRAM cell. We discuss methods to alleviate the read stability fails by enabling the most optimal set of repairs to the highly repairable custom cache arrays without overrunning the total repair capacity of the chip. This paper demonstrates off chip repair calculation strategies to efficiently repair outlier SRAM cells by prioritizing targeted BIST algorithms, test temperature, voltage, and other parameters.
PCI Express (PCIe) is a high-speed interconnect technology that plays crucial role in modern computing systems, connecting key components such as storage devices, network interfaces, accelerators, and GPUs. Ensuring robust interoperability is essential to maintaining device compatibility, link stability, and overall system reliability across different configurations and environments. Rigorous PCIe LTSSM testing helps identify and mitigate link training intermittent failures, signal integrity issues, and protocol mismatches early in development, reducing system downtime, preventing performance degradation, and enhancing user experience. This paper presents a case study on PCIe LTSSM testing in data center class platforms, highlighting real-world test methodologies and issues uncovered in systems.
Implementing Deep Neural Networks (DNNs) in hardware is essential due to rising Power-Performance-Area (PPA) demands and the limitations of GPUs in meeting them. However, such accelerators are vulnerable to Fault Injection Attacks (FIAs), such as those induced by laser illumination or Rowhammer. FAMOUS protects against FIAs by exploiting invariances in DNNs—particularly permutation invariance—by dynamically swapping convolutional channels and linear layer connections during runtime. This misleads attackers aiming to corrupt critical weights that significantly impact model output. We evaluate FAMOUS on transformer models (ViT-tiny and ViT-small) across multiple datasets. Even with 100 faults injected into essential weights, accuracy drops are minimal (≈4.7 and 0.02 points on ImageNet-1k), compared to severe drops (59 and 70 points) without protection. CNNs also benefit from FAMOUS, though to a lesser extent.
The primary purpose of this work is to automate selection of key attributes of a test data compression environment such as Embedded Deterministic Test, the first commercial test compression product. Given a test compression setup, the main objective of the proposed approach is to quickly estimate the expected test pattern count, test data volume, and the resultant test application time within the framework of the actual test compression flow when using ATPG-produced test cubes. This way one can mimic a process of test cube merging and anticipate compressibility of the resultant test patterns without resorting to CPU-intensive ATPG runs and solvers of linear equations. The obtained results, reported herein, are compared with actual stuck-at fault test patterns generated by a commercial test compression tool for several industrial designs in order to validate the proposed model. This allows a final tuning of the new scheme to arrive with a fast and accurate test compression advisement method. It can be used, prior to further steps, to devise the key elements of a test compression ecosystem such as the number of input channels and the size of on-chip test data decompressor.
Traditional structural tests do not provide comprehensive coverage of all possible faults in automotive System-on-Chips (SoCs). To address these gaps, the manufacturing test flow now incorporates System-Level Test (SLT), an additional holistic test phase that executes advanced functional test programs. This research advances SLT methodologies by introducing a stress-optimization approach that targets critical, non-uniformly stressed areas, complementing structural stress methods. It also provides practical guidelines for developing SLT suites that effectively test SoC communication peripherals. Additionally, automated SLT workload generation techniques leverage graph-based SoC abstractions and Device Tree Source (DTS) files to reduce manual effort. Furthermore, grading methodologies are proposed to evaluate SLT effectiveness using high-level metrics derived from instruction traces, enabling early feedback without exhaustive fault simulation. The proposed methods are validated on a 40nm automotive SoC, manufactured by STMicroelectronics, with approximately 20 million logic gates, using a low-cost, FPGA-based modular tester. Experimental results demonstrate that SLT suites can significantly enhance the quality and reliability of automotive SoCs. Collectively, these contributions make SLT more scalable, automated, and effective, meeting stringent automotive quality standards and enabling broader application in domains such as data center processors.
Diagnosis of defects on scan chains is the established methodology for improving semiconductor manufacturing yield throughout the production cycle. The best possible result is to obtain a perfect diagnosis resolution, i.e. identifying a single scan cell per defect. With increased structural complexity and emergence of new production technologies, like backside power, there is a need to improve diagnosis callout beyond single-cell to include transistor-level visibility. In this paper we will present a novel end-to-end software-based methodology for enhancing scan chain diagnosis resolution with cell aware information. The new diagnosis methodology enables the isolation of defects in control signals local to multi-bit register arrays. Volume diagnosis benchmarks and silicon data will be shown to present suspect area improvements that will allow for faster physical failure analysis (PFA) turnaround times.
