In order to reduce the thermal budget for SBT crystallization process in planer type stack cell FeRAMs, Rapid Thermal Anneal (RTA) based process for SBT thin film was investigated. Our new process is characterized by crystallization in RTA without any furnace annealing process, and includes a low temperature recovery annealing process (hereafter RTB (Reduced Thermal Budget) process). As a result of only 750C RTA for accumulated time of 60s without furnace annealing process, the sufficient ferroelectric properties were derived in comparison with that of conventional SBT thin film. In the RTB process, two approaches to improve the break down voltage were carried out. First, we used UV exposure during the baking process. By optimizing the UV assisted baking process, a high break down field due to smooth surface morphology was successfully obtained, resulting in break down field of more than 1.2 MV/cm. Secondly, ultra thin SBT films as a top few layer on the base SBT thin film were employed. After optimization of the ultra thin SBT layer thickness, a very smooth SBT surface was successfully achieved, resulting in improvement of the break down field of more than 1.1 MV/cm.

This letter proposes an enhanced 700 °C process to improve the dielectric breakdown strength and surface roughness of sub-100 nm SrBi2Ta2O9 (SBT) film with a thin (<20 nm) BiTaO4 (BT) layer for the 3 V or lower voltage ferroelectric memory. The process temperature for rapid thermal annealing and furnace annealing is performed at or below 700 °C. The BT layer is used as a capping layer on top of SBT film. It improves the dielectric breakdown strength (1.2 MV/cm) of SBT film without sacrificing other ferroelectric properties.

A 64 Kbit non-destructive readout (NDRO) ferroelectric random access memory (FeRAM) using a 0.6-mum technology is described. The NDRO FeRAM uses a novel linked cell architecture, which minimizes the circuit overhead accepted in Flash memories. This test device has shown 10-year retention and unlimited read operation. An 120-ns NDRO operation is performed at a read voltage of 2.2V. Circuit techniques used in the NDRO FeRAM include: (1) direct programming of ferroelectric capacitors, (2) automatic restoring of read data, and (3) data storing under zero bias conditions. The unique linked cell architecture allows for scaling a cell size down to 6F(2), where F is the minimum feature size available.

A ferroelectric capacitor model was derived, and a ferroelectric device library was implemented into SPICE (both PSPICE and HSPICE) simulation tool. With this SPICE model, 1T-1C/2T-2C, or any other ferroelectric circuit, such as FeFET, chain cell, link cell can be simulated accurately and in real-time. Simulations of hysteresis loops, TVS, switching characteristics are shown in this paper.

Ferroelectric gate MOS capacitors using the "Y-1" family of ferroelectric materials were evaluated. The capacitors were formed by connecting the ferroelectric capacitor and the MIS capacitor in series. The experimental results show the dependence of the memory window on the ferroelectric/insulator capacitance ratios, which gives some useful information on the design of MFSFETs.

SrBi2Ta2O9 based Ferroelectric FETs with a CeO2 buffer layer deposited by Metal Organic Decomposition (MOD) were fabricated on p-Si (100) substrate and analyzed in detail. The hysterisis curve (drain current vs, gate voltage) of the FET shows the counter-clockwise direction, which demonstrates the change of channel conductivity due to the ferroelectric polarization. The memory window with the gate voltage of +/-10V was 2V. The difference of current ratio of I-ds(on) to I-ds(off) was 5 similar to 7 orders in magnitude which is easily sensed by sense amplifiers. The charges of "on" state stored decay logarithmically with time without severe initial loss of data. This indicates the FET-FeRAM can be implemented in NDRO applications.

Functionally graded PZT thin films were deposited via MOD technique by varying Zr/Ti ratio in Pb(Zr,Ti)O-3. Large signal C-V and small signal C-V were measured by using Symetrix Tester. They are found to be asymmetric compared to that of non-graded PZT capacitors and were gradient direction dependent. It's proposed that the built in potential due to graded polarization is the cause of the asymmetry.

By tailoring Zr/Ti ratio in Pb(Zr,Ti)O-3 from 45/55 to 75/25, functionally graded PZT thin films were prepared by metal organic decomposition (MOD) technique. P-E hysteresis loops were measured, and polarization was found to shift up or down depending on the direction of the composition gradients of the PZT. This polarization offset was modeled using Poisson's equation in one dimension. Switching charge was also found to be compositional gradient direction dependent.

Metal/ferroelectric/insulator/semiconduct (MFIS) -structured ferroelectric gate MOS capacitors were fabricated and characterized. The metalorganic decomposition (MOD) technique was employed for the deposition of not only the ferroelectric but also the insulator, which has been usually deposited by e-beam evaporation. The experimental results indicate the usefulness of this technique for the fabrication of this heterostructure, which will accelerate the material research in this field.

Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structure has been fabricated with Strontium Bismuth Tantalate (SBT) ferroelectric and Yttrium oxide as the buffer layer between ferroelectric and silicon. Capacitance versus voltage (C-V) analysis shows that memory window is found to be dependent on charge injection and charge retention in MFIS structure. Analysis of current versus voltage (I-V) characteristics show that the memory window and retention is strongly dependent on the leakage current in the MFIS structure.

Electrical characteristics of Pt-BST-ZrO2-p-Si metal-ferroelectric-insulator-p Si (MFIS) Structures have been investigated. The BST film was deposited by sol gel technique and annealed in oxygen environment for about an hour at 800(0) C. The capacitance-voltage characteristics of these structures show hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The hysteresis in the C-V characteristics were found to be dependent on the thickness of the buffer layer as well as on the duration of the applied voltage. A model based on the polarization of the ferroelectric film and charge injection at the silicon - insulator interface was proposed to explain the electrical characteristics.

Metal Ferroelectric Insulator Semiconductor (MFIS) structure has been fabricated with strontium bismuth tantalate (SBT) as the ferroelectric thin film and zirconium oxide (ZrO2) as the insulating buffer layer. SBT film was deposited by spin-on metal organic deposition (MOD) technique. ZrO2 film was deposited by electron beam evaporation. The capacitance versus voltage characteristics(C-V) of the MFIS structure shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. The C-V characteristics of MFIS structure shows memory window of 1.8 volts for a write/erase voltage of 9V at a sweep rate of 1 sec/1.8V. In order to understand the role of coercive voltage on the memory window in MFIS structures, C-V characteristics metal-ferroelectric metal (MFM) structures with various SBT film thickness' were also studied.