beta-delayed gamma-neutron spectroscopy has been performed on the decay of A=84 to 87 gallium isotopes at the RI-beam Factory at the RIKEN Nishina Center using a high-efficiency array of 3He neutron counters (BRIKEN). beta-2n-gamma events were measured in the decays of all of the four isotopes for the first time, which is direct evidence for populating the excited states of two-neutron daughter nuclei. Detailed decay schemes with the gamma branching ratios were obtained for these isotopes, and the neutron emission probabilities (P-xn) were updated from the previous study. Hauser-Feshbach statistical model calculations were performed to understand the experimental branching ratios. We found that the P-1n and P-2n values are sensitive to the nuclear level densities of 1n daughter nuclei and showed that the statistical model reproduced the P-2n/P-1n ratio better when experimental levels plus shell-model level densities fit by the Gilbert-Cameron formula were used as the level-density input. We also showed the neutron and gamma branching ratios are sensitive to the ground-state spin of the parent nucleus. Our statistical model analysis suggested J <= 3 for the unknown ground-state spin of the odd-odd nucleus Ga-86, from the I gamma(4(+)-> 2(+))/I-gamma(2(+)-> 0(+)) ratio of Ga-84 and the P-2n/P-1n ratio. These results show the necessity of detailed understanding of the decay scheme, including data from neutron spectroscopy, in addition to gamma measurements of the multineutron emitters.

Spectroscopic X-ray imaging techniques including Compton X-ray Imaging, X-ray Fluorescence Imaging and Hyperspectral X-ray Tomography require energy-resolving detectors capable of operating at high incident X-ray fluxes to make time resolved measurements. HEXITECMHz, operates at a continuous 1 MHz frame rate and can make fully spectroscopic measurements at >10(6) ph s(-1) mm(-2). This is enabled by an integrating Front End, in-pixel digitisation and high-speed serialisers. A 300 mu m thick p-type Si HEXITECMHz detector was characterised on the B16 Test Beamline at the Diamond Light Source and are the first measurements taken at a 1 MHz frame rate. At 10 keV and 15 keV) the device displayed average FWHM of 656 eV and 682 eV respectively, with minimal changes in spectroscopic performance over similar to 8 h. Analysis of charge-sharing events show low charge loss and a linear energy-signal response. Higher-flux measurements illustrated the capability of the ASIC to operate as a photon-counting device.

The HEXITEC MHz ASIC is the next generation of the STFC's High Energy X-ray Imaging Technology (HEXITEC). With a ×100 increase in the camera frame rate to 1 MHz, the new ASIC is capable of delivering fully spectroscopic X-ray imaging at photon fluxes of 2×10 6 photons s -1 mm -2 . The improved flux capability ensures the relevance of the technology at a new generation of difraction-limited storage ring (DLSR) synchrotrons as well as enabeling dynamic spectroscopic imaging with sub-keV energy resolution to be carried out on millisecond timescales. In this paper preliminary results from X-ray testing of a 0.3 mm thick p-type Si sensor and 2.0 mm thick HF-CdZnTe sensor at the Diamond Light Source Synchrotron are presented for the first time. Each module consists of 80 × 80 pixels on a 250 μm pixel pitch operated at a temperature of 20°C and a frame rate of 1 MHz. For these preliminary measurements, testing was completed using a prototype test system which limited readout to a portion of the 1 MHz output sampled over an SPI test interface at ∼50 Hz. Despite this limitation these measurements allow the spectroscopic performance of the ASIC to be characterised ahead of the full DAQ system. The prototype detectors were characterised using monochromatic X-rays with energies 12–35 keV at fluxes of (0.6 – 2.5) × 10 6 photons s -1 mm -2 . At an X-ray energy of 12 keV, the energy resolution of the p-type Si and HF-CdZnTe detectors were measured to be 1.0 keV and 1.1 keV respectively. At the higher energies of 20 keV and 35 keV the energy resolution in the HF-CdZnTe was measured to be 1.2 keV and 1.4 keV respectively.

HEXITECMHZ is an ASIC developed to deliver spectroscopic x-ray imaging at frame rates up to 1MHz for future high-flux-rate applications. Optimised for sensing electron signals from detector materials such as CdTe, CZT, GaAs, and p-type silicon detectors, the design has an array of 80×80 pixels on a pitch of 250 μm, with each pixel capable of measuring single x-ray photons up to energies of 200 keV, with a resolution of 1 keV FWHM. Further improvements in the spatial and spectroscopic resolution are possible due to the pixel’s ability to simultaneously sense positive signals up to 20 keV induced by internal weighting-potential effects from electron signals on neighbouring pixels. A count rate limit of around 106 photons s-1 mm-2 is achieved by converting the signals from all pixels every 1 μs using 12-bit time-to-digital converters – an improvement of two orders of magnitude over previous HEXITEC ASICs. To save power, each converter is shared between groups of eight pixels. Each 76.8kbit data frame is Aurora 64b/66b encoded and serialised over twenty lanes of differential CML, all operating in parallel at 4.1 Gbit/s. In this paper, we present details of the design, including preliminary test results from the ASIC.

The HEXITECMHz ASIC has been developed for the HEXITECMHz Detector System, to deliver spectroscopic x-ray imaging at frame rates up to 1 MHz for future high-flux-rate applica-tions. Optimised for sensing electron signals from detector materials such as CdTe, CdZnTe, GaAs and p-type silicon detectors, the design has an array of 80 x 80 pixels on a pitch of 250 mu m, with each pixel capable of measuring single x-ray photons up to energies of 300 keV, with a resolution of 1 keV FWHM. The induced charge signals that are measured by the ASIC will typically be due to the drift of electrons in the sensor material. However, each pixel is also capable of measuring signals of the opposite polarity with magnitudes of up to 20 keV. These events are induced by weighting potential crosstalk and trapping in the sensor and can be exploited in order to provide further improvements in the spatial and spectroscopic performance of the detector. The signals from pixels are digitized every 1 mu s by 12-bit time-to-digital converters. This gives a maximum of 107 photons s-1 mm-2 that can be measured. However, for spectroscopic imaging the occupancy should be limited to 10% in each frame to reduce the charge sharing events. This gives a count rate limit of 106 photons s-1 mm-2 which is two orders of magnitude greater than the previous HEXITEC ASICs. To save power, each converter is shared between groups of eight pixels. Each 76.8 kbit data frame is Aurora 64b/66b encoded and serialised over 20 lanes of differential CML, all operating in parallel at 4.1 Gbps. The ASIC can free run with an asynchronous source or can be synchronized with a pulsed source using the SYNC control input. Expected power consumption is 12-15 W from a 1.8 V supply.

The CMS Binary Chip (CBC) is a front-end ASIC to be used by the CMS tracker following its upgrade for High Luminosity LHC operation. It will instrument special silicon microstrip detectors to identify high transverse momentum particles in real time so tracking data can be used in the L1 trigger. The CBC should be robust against Single Event Upsets (SEUs). SEU rates have been measured in a series of tests in a 62 MeV proton beam. Each version of the chip has increased the digital circuitry, and hence the SEU susceptibility, and has also been subject to design improvements which affect SEU tolerance. The relevant design features are explained and SEU measurements reported. The expected SEU rates at the HL-LHC are estimated.

beta-delayed one-neutron and two-neutron branching ratios (P-1n and P-2n) have been measured in the decay of A = 84 to 87 Ga isotopes at the Radioactive-Isotope Beam Factory (RIBF) at the RIKEN Nishina Center using a high-efficiency array of He-3 neutron counters (BRIKEN). Two-neutron emission was observed in the decay of Ga-84,Ga-85,Ga-87 for the first time and the branching ratios were measured to be P-2n = 1.6(2)%, 1.3(2)%, and 10.2(28)(stat)(5)(sys)%, respectively. One-neutron branching ratio of Ga-87 (P-1n = 81(9)(stat)(8)(sys)%) and half-life of 29(4) ms were measured for the first time. The branching ratios of Ga-86 were also measured to be P-1n = 74(2)(stat)(8)(sys)% and 16.2(9)(stat)(6)(sys)% with better precision than a previous study. The observation that P-1n > P-2n for both Ga-86,Ga-87 was unexpected and is interpreted as a signature of dominating one-neutron emission from the two-neutron unbound excited states in Ge-86,Ge-87. In order to interpret the experimental results, shell-model and Hauser-Feshbach statistical model calculations of delayed particle and gamma-ray emission probabilities were performed. This model framework reproduces the experimental results. The shell model alone predicts P-2n significantly larger than P-1n for the Ga-87 decay, and it is necessary to invoke a statistical description to successfully explain the observation that P-1n > P-2n. Our new results demonstrate the relevance and importance of a statistical description of neutron emission for the prediction of the decay properties of multineutron emitters and that it must be included in the r-process modeling.

The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a consequence a new readout chip is required. In this framework the RD53 collaboration submitted RD53A, a large scale chip demonstrator de- signed in 65 nm CMOS technology, integrating a matrix of 400×192 pixels. It features design variations in the analog and digital pixel matrix for testing purposes. An overview of the building blocks will be given together with test results on single chips.

A new detection system has been installed at the RIKEN Nishina Center (Japan) to investigate decay properties of very neutron-rich nuclei. The setup consists of three main parts: a moderated neutron counter, a detection system sensitive to the implantation and decay of radioactive ions, and gamma-ray detectors. We describe here the setup, the commissioning experiment and some selected results demonstrating its performance for the measurement of half-lives and beta-delayed neutron emission probabilities. The methodology followed in the analysis of the data is described in detail. Particular emphasis is placed on the correction of the accidental neutron background.

A new CMS Tracker is under development for operation at the High Luminosity LHC from 2026 onwards. It includes an outer tracker based on dedicated modules that will reconstruct short track segments, called stubs, using spatially coincident clusters in two closely spaced silicon sensor layers. These modules allow the rejection of low transverse momentum track hits and reduce the data volume before transmission to the first level trigger. The inclusion of tracking information in the trigger decision is essential to limit the first level trigger accept rate. A customized front-end readout chip, the CMS Binary Chip (CBC), containing stub finding logic has been designed for this purpose. A prototype module, equipped with the CBC chip, has been constructed and operated for the first time in a 4 GeV/c positron beam at DESY. The behaviour of the stub finding was studied for different angles of beam incidence on a module, which allows an estimate of the sensitivity to transverse momentum within the future CMS detector. A sharp transverse momentum threshold around 2 GeV/c was demonstrated, which meets the requirement to reject a large fraction of low momentum tracks present in the LHC environment on-detector. This is the first realistic demonstration of a silicon tracking module that is able to select data, based on the particle's transverse momentum, for use in a first level trigger at the LHC . The results from this test are described here.

The High Energy X-ray Imaging Technology (HEXITEC) ASIC is designed on a 0.35 μm CMOS process to read out CdTe or CZT detectors and hence provide fine-pixellated spectroscopic imaging in the range 2–200 keV. In this paper, we examine the tolerance of HEXITEC to both potentially destructive cumulative and single event radiation effects. Bare ASICs are irradiated with X-rays up to a total ionising dose (TID) of 1 Mrad (SiO2) and bombarded with heavy ions with linear energy transfer (LET) up to 88.3 MeV mg−1 cm−2. HEXITEC is shown to operate reliably below a TID of 150 krad, have immunity to fatal single event latchup (SEL) and have high tolerance to non-fatal SEL up to LETs of at least 88.3 MeV mg−1 cm−2. The results are compared to predictions of TID and SELs for various Earth-orbits and aluminium shielding thicknesses. It is found that HEXITEC's radiation tolerance to both potentially destructive cumulative and single event effects is sufficient to reliably operate in these environments with moderate shielding.

A pair of radiation hardened high-voltage mixed signal Application Specific Integrated Circuits (ASICs) are described that provide the biasing and clocking functions required to drive large format CCDs used for space-borne cameras and focal planes. The use of these ASICs allows the CCD drive electronics to be realised in a compact and energy efficient manner saving volume, mass, and power when compared with traditional space-qualified discrete implementations. The STAR ASIC provides 24 independent voltage outputs with a 32.736V range at 10 bit resolution and with <100μV noise. Each voltage output provides a drive current of up to +/-20mA and is stable for capacitive loads of up to 10μF. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows internal monitoring of the output voltages plus up to 32 single ended and 4 differential external voltages, such as from PRT bridge circuits for temperature monitoring. A simple SPI serial interface provides control and telemetry read back, while all required voltages and currents are generated from internal bandgap circuits. The COMET ASIC provides 6 fully independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and output slew rate required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is also via an SPI interface with integrated safety features to ensure correct sequencing of channel operation and to prevent reverse biasing of the driver programmable voltage supplies. The COMET ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of unexpected power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. Both devices have been designed in a commercial 0.35μm 50V tolerant HV CMOS technology using Triple Module Redundancy (TMR) and established layout techniques to harden against Total Ionising Dose (TID), Single Event Upset (SEU), and Single Event Latch-up (SEL) radiation effects. The latch-up detection circuits often needed for space electronics are therefore not required for either ASIC. Details of the architectures and circuit implementations of both ASICs will be presented. Test results from manufactured devices will be shown under representative load conditions.

R3B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R3B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements.

Thought to produce around half of all isotopes heavier than iron, the r-process is a key mechanism for nucleosynthesis. However, a complete description of the r-process is still lacking and many unknowns remain. Experimental determination of beta-decay half-lives and beta-delayed neutron emission probabilities along the r-process path would help to facilitate a greater understanding of this process. The Advanced Implantation Detector Array (AIDA) represents the latest generation of silicon implantation detectors for beta-decay studies with fast radioactive ion beams. Preliminary results from commissioning experiments demonstrate successful operation of AIDA and analysis of the data obtained during the first official AIDA experiments is now under-way.

The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker.The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates.The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested.The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic.Finally we will outline the plan for future developments towards the production version.

The development of new experiments such as CLIC and the the foreseen Phase 2 pixel upgrades of ATLAS and CMS have very challenging requirements for the design of hybrid pixel readout chips, both in terms of performances and reliability. To face these challenges, the use of a more downscaled CMOS technology compared to previous projects is necessary. The CERN RD53 collaboration is undertaking a R&D programme to evaluate the use of a commercial 65 nm technology and to develop tools and frameworks which will help to design future pixel detectors. This paper gives a short overview of the RD53 collaboration activities and describes some examples of recent developments.

The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

A 130 nm CMOS chip has been designed for silicon microstrip readout at the SLHC. The CBC has 128 channels, and utilises a binary un-sparsified architecture for chip and system simplicity. It is designed to read out signals of either polarity from short strips (capacitances up to ~ 10 pF) and can sink or source sensor leakage currents up to 1 μA. Details of the design and measured performance are presented.

We present the development and prototype test of the LPD instrument, a novel pixel detector for the European XFEL. At XFEL the LPD detector must be capable of operating with a frame rate of 4.5MHz and record images with a dynamic range of 1:100,000 photons (12keV) whilst maintaining low noise. The prototype LPD system has a large in pixel memory depth of 512 images that can be selected with a flexible veto system. Data is then transferred off the detector head in between XFEL pulses with an accompanying high rate data acquisition system. The system has been prototyped and assembled into an LPD detector head that contains custom silicon sensors and ASICs as well as a programmable data acquisition cards and supporting electronics and mechanics. A second version of the ASIC has also been submitted for manufacture. The experiences with our first prototype are presented.