In this paper, results are presented from the characterisation of Redlen Technologies high-flux-capable Cadmium Zinc Telluride (HF-CZT) hybridised to the HEXITECMHz ASIC, a novel 1 MHz continuous X-ray imaging system. A 2 mm thick HF-CZT HEXITECMHz detector was characterised on the B16 Test Beamline at the Diamond Light Source and displayed an average FWHM of 850 eV for monochromatic X-rays of energy 20 keV. Measurements revealed a shift in the baseline of irradiated pixels that results in a movement of the entire spectrum to higher ADU values. Datasets taken to analyse the effect's dynamics showed it to be highly localised and flux-dependent, with the excess leakage current generated equivalent to per-pixel shifts of similar to 543 pA (8.68 nA mm(-2)) at a flux of 1.26x10(7) ph s(-1) mm(-2). Comparison to results from a p-type Si HEXITECMHz device indicate this `excess leakage-current' effect is unique to HF-CZT and it is hypothesised that it originates from trapping at the electrode-CZT interface and a temporary modification of the potential barrier between the CZT and metal electrode.

Spectroscopic X-ray imaging techniques including Compton X-ray Imaging, X-ray Fluorescence Imaging and Hyperspectral X-ray Tomography require energy-resolving detectors capable of operating at high incident X-ray fluxes to make time resolved measurements. HEXITECMHz, operates at a continuous 1 MHz frame rate and can make fully spectroscopic measurements at >10(6) ph s(-1) mm(-2). This is enabled by an integrating Front End, in-pixel digitisation and high-speed serialisers. A 300 mu m thick p-type Si HEXITECMHz detector was characterised on the B16 Test Beamline at the Diamond Light Source and are the first measurements taken at a 1 MHz frame rate. At 10 keV and 15 keV) the device displayed average FWHM of 656 eV and 682 eV respectively, with minimal changes in spectroscopic performance over similar to 8 h. Analysis of charge-sharing events show low charge loss and a linear energy-signal response. Higher-flux measurements illustrated the capability of the ASIC to operate as a photon-counting device.

The HEXITECMHz ASIC has been developed for the HEXITECMHz Detector System, to deliver spectroscopic x-ray imaging at frame rates up to 1 MHz for future high-flux-rate applica-tions. Optimised for sensing electron signals from detector materials such as CdTe, CdZnTe, GaAs and p-type silicon detectors, the design has an array of 80 x 80 pixels on a pitch of 250 mu m, with each pixel capable of measuring single x-ray photons up to energies of 300 keV, with a resolution of 1 keV FWHM. The induced charge signals that are measured by the ASIC will typically be due to the drift of electrons in the sensor material. However, each pixel is also capable of measuring signals of the opposite polarity with magnitudes of up to 20 keV. These events are induced by weighting potential crosstalk and trapping in the sensor and can be exploited in order to provide further improvements in the spatial and spectroscopic performance of the detector. The signals from pixels are digitized every 1 mu s by 12-bit time-to-digital converters. This gives a maximum of 107 photons s-1 mm-2 that can be measured. However, for spectroscopic imaging the occupancy should be limited to 10% in each frame to reduce the charge sharing events. This gives a count rate limit of 106 photons s-1 mm-2 which is two orders of magnitude greater than the previous HEXITEC ASICs. To save power, each converter is shared between groups of eight pixels. Each 76.8 kbit data frame is Aurora 64b/66b encoded and serialised over 20 lanes of differential CML, all operating in parallel at 4.1 Gbps. The ASIC can free run with an asynchronous source or can be synchronized with a pulsed source using the SYNC control input. Expected power consumption is 12-15 W from a 1.8 V supply.

The CMS Binary Chip (CBC) is a front-end ASIC to be used by the CMS tracker following its upgrade for High Luminosity LHC operation. It will instrument special silicon microstrip detectors to identify high transverse momentum particles in real time so tracking data can be used in the L1 trigger. The CBC should be robust against Single Event Upsets (SEUs). SEU rates have been measured in a series of tests in a 62 MeV proton beam. Each version of the chip has increased the digital circuitry, and hence the SEU susceptibility, and has also been subject to design improvements which affect SEU tolerance. The relevant design features are explained and SEU measurements reported. The expected SEU rates at the HL-LHC are estimated.

The CBC3 is the latest version of the CMS Binary Chip for readout of the outer radial region of the upgraded CMS Tracker at the High Luminosity LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, containing two overlaid silicon microstrip sensors, aligned with a parallel orientation. On-chip logic identifies Level-1 trigger primitives from high transverse-momentum tracks by selecting correlated clusters in the two sensors. The CBC3 was delivered in late 2016; wafer probing and performance tests have been carried out. Several prototype modules using the CBC3 have been produced and tested in the lab and in different beams. The results show that the CBC3 satisfies CMS requirements and only small corrections are needed for the final version of the chip for production.

The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC.This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded.It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips.On-chip logic identifies first level trigger primitives from high transversemomentum tracks by selecting correlated hits in the two sensors.Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing.Results and performance are reported.

The High Energy X-ray Imaging Technology (HEXITEC) ASIC is designed on a 0.35 μm CMOS process to read out CdTe or CZT detectors and hence provide fine-pixellated spectroscopic imaging in the range 2–200 keV. In this paper, we examine the tolerance of HEXITEC to both potentially destructive cumulative and single event radiation effects. Bare ASICs are irradiated with X-rays up to a total ionising dose (TID) of 1 Mrad (SiO2) and bombarded with heavy ions with linear energy transfer (LET) up to 88.3 MeV mg−1 cm−2. HEXITEC is shown to operate reliably below a TID of 150 krad, have immunity to fatal single event latchup (SEL) and have high tolerance to non-fatal SEL up to LETs of at least 88.3 MeV mg−1 cm−2. The results are compared to predictions of TID and SELs for various Earth-orbits and aluminium shielding thicknesses. It is found that HEXITEC's radiation tolerance to both potentially destructive cumulative and single event effects is sufficient to reliably operate in these environments with moderate shielding.

A pair of radiation hardened high-voltage mixed signal Application Specific Integrated Circuits (ASICs) are described that provide the biasing and clocking functions required to drive large format CCDs used for space-borne cameras and focal planes. The use of these ASICs allows the CCD drive electronics to be realised in a compact and energy efficient manner saving volume, mass, and power when compared with traditional space-qualified discrete implementations. The STAR ASIC provides 24 independent voltage outputs with a 32.736V range at 10 bit resolution and with <100μV noise. Each voltage output provides a drive current of up to +/-20mA and is stable for capacitive loads of up to 10μF. An on-board telemetry system featuring a 12-bit ADC and programmable gain buffer allows internal monitoring of the output voltages plus up to 32 single ended and 4 differential external voltages, such as from PRT bridge circuits for temperature monitoring. A simple SPI serial interface provides control and telemetry read back, while all required voltages and currents are generated from internal bandgap circuits. The COMET ASIC provides 6 fully independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and output slew rate required over a 409.6mA range, with edge speeds <15ns achievable for small loads. Setup and control of the ASIC is also via an SPI interface with integrated safety features to ensure correct sequencing of channel operation and to prevent reverse biasing of the driver programmable voltage supplies. The COMET ASIC also features an under-voltage lock out circuit to safeguard the chip in the event of unexpected power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. Both devices have been designed in a commercial 0.35μm 50V tolerant HV CMOS technology using Triple Module Redundancy (TMR) and established layout techniques to harden against Total Ionising Dose (TID), Single Event Upset (SEU), and Single Event Latch-up (SEL) radiation effects. The latch-up detection circuits often needed for space electronics are therefore not required for either ASIC. Details of the architectures and circuit implementations of both ASICs will be presented. Test results from manufactured devices will be shown under representative load conditions.

This paper discusses a compressed-ROM 600MSPS dual-branch Direct Digital Synthesizer (DDS) providing sinewaves of <;150MHz with 2μHz resolution and SFDR >80dBc. It supports positive chirp slopes up to 40MHz/s with ~1.3kHz/s resolution. The amplitude can be shaped with Gaussian envelopes of FWHM 2μs-2ms and SLRR >85dB. Any other envelope can be generated by pulsing programmable-step increment/decrements through dedicated LVDS inputs. The ASIC delivers two 14-bit 300MSPS LVDS buses to interface with an external DAC using a ping-pong arrangement. The output data is synchronous to a DDR clock coming from the DAC, which can pass through a programmable delay-line to adjust the loop phase. A demonstrator chip was manufactured in 0.18μm CMOS process.

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA’s Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD’s bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0–32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1–2 MHz and image clock frequencies in the range 10–100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

R3B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R3B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements.

A high voltage mixed signal ASIC is described that provides multiple fully programmable clock outputs capable of driving large format CCD capacitive electrodes. The COMET ASIC provides 6 independent clock buffering channels each with individually programmable rising/falling current drive and high/low voltage levels. Output voltage levels are controlled with integrated fast response regulators that operate over a 16.368V range without the need for external decoupling capacitors. Clock drive currents can be adjusted for the load capacitance and voltage swing required over a 409.6mA range, with edge speeds < 15ns achievable for small loads. Setup and control of the ASIC is via a simple SPI interface with safety features to ensure correct sequencing of channel operation and prevent driver supply reverse biasing. The ASIC also features an under- voltage lock out circuit to safeguard the chip in the event of power loss. All necessary biases are generated internally and only supply decoupling, a single filtering capacitor, and a resistive divider are required to operate the device. The circuit is manufactured in a commercial 0.35um HV CMOS technology and uses established layout techniques to harden against both Total Ionising Dose (TID) and Single Event Latchup (SEL) radiation effects. The device has been manufactured and test results are shown.

A 128-channel event-driven ASIC is described which reads out the R 3 B (Reactions with Relativistic Radioactive Beams) silicon micro vertex tracker. Ionizing particles with energies in the range of 40keV-50MeV are detected, digitized and read out with 12 bit resolution, and time stamped with up to 5ns precision. The ASIC copes with signal charges and detector leakage currents of both polarities and allows charge sharing to be taken into account by reading out the charge from neighboring channels. The ASIC can recover quickly from signals up to 1Gev, can store up to 32 events and can be easily daisy-chained to reduce parallel connections. Outputs can be Manchester encoded to allow for capacitive coupling of the data, and a 128-bit OR of all the channel hits provides a fast trigger output.

The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

We present the design of CBC2, the new version of the CMS Binary Chip ASIC for the readout of CMS Tracker Phase-two upgrade. CBC2, designed in 130nm CMOS, doubles the input channels to 254 and will be bump-bonded to the substrate. The ASIC is designed to instrument double layer modules in the outer tracker, consisting of two overlaid silicon sensors with aligned microstrips, and incorporates the logic to identify L1 trigger primitives in the form of ``stubs'': high transverse-momentum candidates which are isolated from the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The functionality of the coincidence logic, which includes rejection of wide clusters and offset correction to account for the position of the module in the R-ϕ plane, is described in detail.

We are developing CMOS Monolithic Active Pixel Sensors for particle physics. A family of sensors, RAL_HEPAPS, has been developed. The first three sensors of this family were parametric test sensors, on which different types of pixel architectures were integrated. These sensors were designed, manufactured and tested and recent results obtained by our collaboration will be briefly reviewed. The latest sensor in the family, RAL_HEPAPS4, is the first step towards a large-area sensor as required for particle physics. It has 1026×384 pixels with a pixel pitch of 15μm, for a total sensing area of 15.39×5.76mm2. The line rate can be in excess of 5MHz, which, for column parallel readout, would yield an equivalent 76μs full frame readout time. Three different versions of the RAL_HEPAPS4 were produced, with the same global architecture but with different diode structures. The design and simulated performances will be reviewed.

This paper describes the design and operation of a low noise analogue readout system for X-ray CCDs (at up-to 1MHz pixel rate) for e2v's CCDs. A major part of the system is Correlated Double Sampler (CDS) Application Specific Integrated Circuit (ASIC) designed in collaboration with the CCLRC. Here we discuss the ASIC specification, design and applications, together with the measured performance.