A new integrated-process approach is introduced enabling precision control and co-optimization of advanced gate stacks delivering 1-2 Å EOT scaling while maintaining same gate leakage level compared to a traditional flow. We demonstrated this Tinv oxide integrated scaling on advanced FinFET test vehicles and show > 8% I on /I off gain for SiGe Fin PFET / Si Fin NFET, and similar benefits are preliminarily observed on Nano-Sheet (NS) devices. This paves the way for current and next generation CMOS devices for scaling and performance improvement.

A brief introduction reviews the changes that have occurred in semiconductor wafer processing, which, coupled with developments in X ray Photoelectron Spectroscopy, XPS, instrumentation, have led to XPS becoming a primary materials analysis tool in this industry. Three specific examples illustrating the use of XPS and Angle resolved XPS, ARXPS, are then presented. These are nitridation processing of high k gate material (HfO2 based); the monitoring of Al content and chemistry in a 10A TiAlN film (a metal gate add on process to high k); and deposition of diamond-like amorphous C films (a candidate for hard mask applications in DRAM, NAND flash, and NOR flash memories).

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO 2 was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N 2 O/H 2 was also varied from 5Å to 10Å. The threshold voltage (V th ) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.

World class EOT scaling and reliability performance has been achieved by integration (no air-break) of thermal interface layer (IL) and ALD high-k. RTP process is used for the formation of Ultra-Thin IL (UT-IL) and Mono-Layer IL (ML-IL). While integrated with ALD HfOx process, the resultant dielectric stack can reach 6Å EOT with excellent gate leakage, mobility and BTI reliability performances. The experiment also demonstrates that integrated thermal IL/HfOx stack provides lower pre-existing trap density and lower trap generation during BTI when compared to conventional chemical oxide IL/air-beak/HfOx stack.

NBTI and PBTI are studied in IL/HK/MG gate stacks having EOT down to ~ 6Å and fabricated using low T RTP based thermal IL and a novel IL/HK integration. At equivalent EOT, proposed stacks provide improved NBTI and similar PBTI when compared to conventional Chem-Ox IL based HKMG stacks. EOT scaling achieved by RTP thermal IL scaling shows lower rate of increase in NBTI and PBTI when compared to Chem-Ox IL scavenged stacks. Impact of Nitrogen and role of post HK nitridation are studied. Physical mechanism of improved BTI in proposed stacks is discussed in detail.

Rapid thermal annealing in nitric oxide (RTNO) has long been used for the formation of ultrathin silicon oxynitride gate dielectrics. Nitric oxide (NO) furnace anneals are used in the formation of floating gate Flash memory transistor tunnel oxides. Nitrogen is thus, incorporated to improve the oxide reliability during program/erase cycling endurance and data retention. We present here a study of rapid thermal annealing and oxide growth in nitric oxide using Applied Materials single-wafer rapid thermal process (RTP) that enables the RTNO anneal to operate at higher temperatures compared to furnace, thereby allowing two times greater incorporation of nitrogen at the silicon/silicon dioxide interface. At 1200°C, a greater than 11% peak interface nitrogen concentration as measured by secondary ion mass spectroscopy (SIMS) in a 75 Angstrom SiON film is achieved. Reliability testing using a floating gate flash memory capacitor with minority carrier source (implants) test vehicle shows that this increase in the peak interface nitrogen results in an improvement in the tunnel oxide's program/erase cycling endurance and data retention. For future memory devices, for example 3D memory devices, the use of direct RTNO oxide growth for dielectric formations is possible. In this case, higher temperatures allow the growth of thicker oxides in pure NO at 1200°C, with greater nitrogen incorporation.

High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS. Sub-32nm targets are reached by integrating the high-k with a scaled interface layer (iL), post HK nitridation and anneal. The quality of the HK bulk material and it's interface with the iL plays a critical role in the transistor's reliability degradation. This paper investigates the reliability benefits of clustering the different HK stack process chambers on a single tool without a vacuum break. It was found that full clustering of the iL + HK + nitridation steps provides the most scalable and reliable gate stack.