ULTRARAM is an emerging memory technology exhibiting high endurance ($\gt10^{7} \mathbf{P} / \mathbf{E}$ cycles), ultra-high retention ($\gt1000$ years), and ultra-low switching energy per unit area. This compound-semiconductor-based non-volatile memory (NVM) works on the principle of triple-barrier resonant tunneling (TBRT) using InAs/AlSb heterostructures. Single memory cells have been fabricated on GaAs and Si substrates. A physicsbased compact model is proposed to accurately capture the realtime trapping/de-trapping of charges in the floating gate (FG) and utilized for synapse simulations. Benchmarking with other emerging memories highlight the promise of this technology as a next-generation non-volatile memory. Specifically, a circuit-level macro-model is employed to evaluate and benchmark the onchip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core.

The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal-oxide-semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance ( > 10 7 P/E cycles), ultrahigh retention ( > 1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8 & times; and 1.52 & times;, respectively, with 91% of training accuracy.

ULTRARAM is a promising emerging memory exhibiting high endurance, long retention, and ultra-low switching energy per unit area. This compound semiconductor-based non-volatile memory utilizes triple barrier resonant tunneling (TBRT) through InAs/AlSb heterostructures. In this work, we have proposed a physics-based compact model of ULTRARAM memory device that captures the real-time trapping/de-trapping of charges in the floating gate and used to calculate the device characteristics. In addition, we have performed numerical simulations of the TBRT stack using the Schr & ouml;dinger equation inside the quantum well with mono-layer ( similar to 0.6 nm) variations to check the impact on memory characteristics of the device. Array-level simulations and benchmarking highlight the promise of this technology. (c) 2025 Author(s). All article content, except where otherwise noted, is licensed under a Creative Commons Attribution (CC BY) license

Highly mismatched III/V alloys, such as GaAsN and GaAsSb, are known to suffer from segregation and clustering effects, which often limit their application in devices. In this cross-sectional scanning tunneling microscopy (X-STM) study, we explore the atomic-scale behavior of iso-electronic Sb doping atoms in MBE-grown dilute GaAs1-xSbx (0.01 < x < 0.03). We found that Sb atoms up to four layers below the cleavage surface can be identified in filled-state X-STM images. They appear with diverse anisotropic contrasts, depending on the depth of the Sb atom. These features are classified and are related to their depth below the cleavage surface through careful symmetry considerations. We show that the depth-dependent contrast of Sb atoms in filled-state imaging is determined by both topographic effects (lattice deformation due to the large Sb atom) and electronic effects (resonances of Sb atoms in the valence band). This study shows that in MBE-grown GaAsSb alloys, the Sb atoms can be rapidly incorporated, in which case the GaAsSb layers suffer little from segregation and sharp interfaces can be obtained. Additionally, short-range ordering of Sb, which can be uniquely studied by X-STM, has been analyzed in terms of nearest-neighbor-pair formation, and we find that in MBE-grown GaAsSb materials, a tendency to form Sb pairs or clusters can be suppressed. This opens the route to create high-quality devices based on the highly mismatched GaAsSb alloy.

Renewed interest in vertical-cavity surface-emitting lasers (VCSELs) operating in the regions of 1300 and 1550 nm has come as a result of the desire for so-called 'eye-safe' lasers (>1400 nm) in consumer applications, for below-screen sensing in mobile devices (>1380 nm) and for light detection and ranging (LiDAR). Current VCSELs have a host of applications, including printing, bar code reading, data communications and facial recognition systems. Typical (In)GaAs quantum-well VCSEL active-regions are sub-optimal for reaching telecoms and 'eye-safe' wavelengths because of the large strain accompanying the increased In fraction required. Here, a case is made for the use of GaSb quantum rings (QRs) over other materials in VCSEL active regions for devices across the telecoms range. The design and fabrication of two prototype quantum ring VCSELs is discussed and provisional results are presented for continuous operation at room temperature and at 77 K. The origin of background emission is considered and a sub-milliamp threshold current achieved for emission at 1257 nm.

An easy to fabricate ohmic-contact to moderately-doped p-type GaAs has been achieved. The tri-layer Au/Ni/Au contact is deposited by thermal evaporation, followed by rapid thermal annealing in nitrogen atmosphere. A series of annealing times and temperatures are explored to determine the influence of annealing conditions on the low-resistance ohmic contacts. The resulting contacts show more than three orders of magnitude reduction in contact resistance compared to alternative Ti/Au depositions.

ULTRARAM(TM) is a novel floating-gate nonvolatile memory in which the oxide barrier of flash is replaced by a triple-barrier resonant tunneling structure comprising of multiple InAs/AlSb heterojunctions. The quality of the triple barrier resonant tunneling heterostructure of an ULTRARAMTM device in terms of interface sharpness and the presence of defects was analyzed by cross-sectional scanning tunneling microscopy. We observed two different types of defects: stacking faults originating in the layers below the triple barrier resonant tunneling structure and AlSb accumulations at the interface between the lower AlSb layer of the triple barrier resonant tunneling structure and the InGaAs channel. The InGaAs surface of a second sample was measured by atomic force microscopy in order to investigate whether its unevenness is caused by deposition of the AlSb layer or it is already present before the AlSb deposition process.

ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow‐energy electron storage in a floating gate accessed through a triple‐barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost‐effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single‐cell memories show clear 0/1 logic‐state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation‐free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.

ULTRARAM™ is a III–V semiconductor memory technology which allows non-volatile logic switching at ultra-low energy (per unit area). This is achieved by exploiting triple-barrier resonant tunnelling (TBRT) through a series of InAs/AlSb heterojunctions specifically engineered for this purpose. Electrons tunnelling through the barriers at low bias are trapped in a floating gate, in which the presence or absence of charge defines the memory logic. Here, we report detailed non-equilibrium Green’s functions simulations of the InAs/AlSb TBRT heterostructure, which is the principal source of ULTRARAM™’s extraordinary performance benefits. The effects of variations to the heterostructure layer thickness are investigated for performance optimization, and for assessing growth and process tolerances for commercial implementation on 12″ Si wafers. Trade-offs between power, speed, logic disturbance and data retention time are identified. Importantly, most one monolayer alterations to the tunnelling region show the required characteristics for ULTRARAM™ memory operation, thus some tolerance in any future commercial fabrication process is identified.

ULTRARAM is a III–V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a $2\times2$ memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500- $\mu \text{s}$ duration, a remarkable switching speed for a $20~ \mu \text{m}$ gate length. Memory retention is tested for $8\times 10^{4}$ s, whereby the 0/1 states show adequate contrast throughout, whilst performing $8\times 10^{4}$ readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for $10^{6}$ cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over $10^{5}$ half-voltage cycles.

ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al2O3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×103 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 104 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >105 P/E disturbances.

Dynamic random-access memory (DRAM), which represents 99% of random-access memory (RAM), is fast and has excellent endurance, but suffers from disadvantages such as short data-retention time (volatility) and loss of data during readout (destructive read). As a consequence, it requires persistent data refreshing, increasing energy consumption, degrading performance, and limiting scaling capacity. It is, therefore, desirable that the next generation of RAM will be nonvolatile RAM (NVRAM), have low power, have high endurance, be fast, and be nondestructively read. Here, we report on a new form of NVRAM: a compound-semiconductor charge-storage memory that exploits quantum phenomena for its operational advantages. Simulations show that the device consumes very little power, with 100 times lower switching energy per unit area than DRAM, but with similar operating speeds. Nonvolatility is achieved due to the extraordinary band offsets of InAs and AlSb, providing a large energy barrier (2.1 eV), which prevents the escape of electrons. Based on the simulation results, an NVRAM architecture is proposed for which extremely low disturb-rates are predicted as a result of the quantum-mechanical resonant-tunneling mechanism used to write and erase.

A 6-period GaAs/Al 0.9 Ga 0.1 As distributed Bragg reflector (DBR) has been grown and its optical properties have been both measured and simulated. Incremental improvements were made to the simulation, allowing it to account for internal consistency error, incorrect layer thicknesses, and absorption due to substrate doping to improve simulation accuracy. A compositional depth profile using secondary-ion mass spectrometry (SIMS) has been taken and shows that the Al fraction averages 88.0% ± 0.3%. It is found that the amplitude of the transmission is significantly affected by absorption in the n-doped GaAs substrate, even though the energy of the transmitted light is well below the GaAs band gap. The wavelength of the features in the transmission spectrum are mostly affected by DBR layer thicknesses. On the other hand, the transmission spectrum is found to be relatively tolerant to changes to Al fraction.

ULTRARAMTM is a novel memory technology that potentially combines the non-volatility of flash with performance that exceeds DRAM. We review the motivation for an ultra-efficient non-volatile memory for autonomous Internet of Things sensors and the state of the art in memory technology. We describe progress in ATTRACT Phase 1 in second generation devices, arrays and growth on Si substrates. For ATTRACT Phase 2 we propose a dramatic advance in the technology to ≥100 Mbit chips and three technology demonstrators. This ambitious goal is based on the rapid progress to date, on-going funding and strong industrial interest in the technology.

Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10 4 s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.

Excitonic complexes in type-II quantum-ring heterostructures may be considered as artificial atoms due to the confinement of only one charge-carrier type in an artificial nucleus. Binding energies of excitons, trions, and biexcitons in these nanostructures are then effectively ionization energies of these artificial atoms. The binding energies reported here are calculated within the effective-mass approximation using the diffusion quantum Monte Carlo method and realistic geometries for gallium antimonide rings in gallium arsenide. The electrons form a halo outside the ring, with very little charge density inside the central cavity of the ring. The de-excitonization and binding energies of the complexes are relatively independent of the precise shape of the ring.

We report the controllable growth of GaAs quantum complexes in droplet molecular-beam epitaxy, and the optical properties of self-assembled AlxGa1-xAs quantum rings embedded in a superlattice. We found that Ga droplets on a GaAs substrate can retain their geometry up to a maximum temperature of 490 degrees C during post-growth annealing, with an optimal temperature of 320 degrees C for creating uniform and symmetric droplets. Through controlling only the crystallisation temperature under As-4 in the range of 450 degrees C to 580 degrees C, we can reliably control diffusion, adsorption and etching rates to produce various GaAs quantum complexes such as quantum dots, dot pairs and nanoholes. AlxGa1-xAs quantum rings are also realised within these temperatures via the adjustment of As beam equivalent pressure. We found that crystallisation using As-2 molecules in the place of As-4 creates smaller diameter quantum rings at higher density. The photoluminescence of As-2 grown AlxGa1-xAs quantum rings embedded in a superlattice shows a dominant emission from the quantum rings at elevated temperatures. This observation reveals the properties of the quantum ring carrier confinement and their potential application as efficient photon emitters.

Mobilities and carrier densities of modulation doped Al0.2Ga0.8Sb/GaSb heterostructures are presented for the first time. The structures studied were grown by molecular beam epitaxy and consisted of a single heterojunction with Te compensation doping to reduce the intrinsic p-type background. Hall measurements were performed from 30-300 K, giving p-type mobilities peaking at 3240 cm(2)/Vs, a considerable improvement over previous reported bulk mobilities for samples with compensation doping. Growth trials on bulk material have also been carried out to investigate the optimum growth conditions for future structures, with the aim of minimising the occurrence of natural growth defects in GaSb, which act as acceptors. Together these measurements lay the ground work for (magneto)transport studies of two-dimensional charge-carriers in AlxGa1-xSb/GaSb heterostructures, which has not been previously reported.