In this paper, the authors present an innovative ultra-low-power IoT-Core that can be used as an extension for efficient DC/DC converters. The module equips the overall system with computation and communication capabilities for Industry 4.0 and IIoT applications without adding significant power requirements. The research focuses on optimizing energy consumption by taking an overarching view of hardware and software at the system level. In the active state, the IoT-Core can adjust its power consumption at runtime by matching the application demands to the existing energy budget. In sleep state, the module uses a novel Wake-Up Receiver in the 868 MHz frequency band with an average power consumption of 3.5muW, allowing the system to wake up in 32ms. The results are demonstrated on a DC/DC converter, with an efficiency of up to 99.8%, which uses the plug-and-play IoT-Core to become a smart device that can save additional energy when being in idle mode.

This paper proposes a frequency agile fully integrated super-regenerative receiver for spectral power estimation. A 180-nm implementation of the proposed receiver is presented with measurements. The receiver draws 26 μA from a 1.8 Volt supply to scan 60 frequency points between 380 and 960 MHz every 1.8 ms, hence 780 nW per channel. The “resolution bandwidth” lies between 2 and 15 MHz, depending on the quench-signal. No external filter components are used. Filter quality factors greater than 400 are achieved, using an on-chip inductor. The best measured receiver sensitivity is -75 dBm.

This paper introduces a novel approach for ultra-low-power radio receivers based on Armstrong's super-regenerative architecture. With a power consumption of 1 μW or less the receiver presents a big improvement to the state-of-the-art of 400 μW. In consequence, low maintenance wireless networks are much more feasible. Receiver sensitivity is measured -90 dBm. Spurious emissions from the oscillator are suppressed below -100 dBm, such that the receiver is suitable for wireless sensor networks with high nodal density. Dynamic co-channel interferers are tolerated instantaneously by means of parallel processing and forward error correction.

An ultra-low power wake-up receiver for 2.4-GHz wireless sensor networks, based on a fast sampling method, is presented. A novel multi-branch receiver architecture covers a wide range of interferer scenarios for highly occupied radio channels. The scalability of current consumption versus data rate at a constant sensitivity is another useful feature that fits a multitude of applications, requiring both short reaction times and ultra-low power consumption. The 2.4-GHz OOK receiver comprises a 3-branch analog superheterodyne front-end and six digital 31-bit correlating decoders. It is fabricated in a 130-nm CMOS technology. The current consumption is 2.9 μA at 2.5 V supply voltage and a reaction time of 30 ms. The receiver sensitivity is -80 dBm. Among other sub-100 μW state-of-the-art receivers, the presented implementation shows the best reported sensitivity.

A ultra-low power wake-up receiver based on a novel fast sampling method is presented. The innovative approach allows the scalability of current consumption versus data rate at a constant sensitivity, meeting both short reaction time and ultra-low power consumption requirements. The 868 MHz OOK receiver comprises an analogue superheterodyne front-end and two digital 31 bit correlating decoders. It is fabricated in a 130 nm CMOS technology. The current consumption of the prototype is 1.2 μA at 2.5 volts supply voltage and a reaction time of 484 ms. The receiver sensitivity is -83 dBm thus obtaining a line-of-sight distance of 1200 metres for an assumed transmit power of 10 mW. Compared to other sub-100 μW receivers, the sensitivity of the presented implementation is best.

This paper presents the overall architecture, first test structure implementations, and measurement results of an integrated GNSS front-end based on intentional path overlay. The front-end ASIC supports simultaneous multiband, multi-system GNSS reception of GPS L5 / Galileo E5 / GLONASS G3 and GPS L1 / Galileo E1 / GLONASS G1 signals with up to 52MHz bandwidth while using only one common baseband path thanks to an intentional analog signal overlay. Test structures of the RF and baseband parts were realized in a 1.8 V, 150nm RF-CMOS technology packaged in a QFN48 housings with full ESD protection. Both chips are described in detail regarding their design and their actual measurement results.