In this paper, the authors present an innovative ultra-low-power IoT-Core that can be used as an extension for efficient DC/DC converters. The module equips the overall system with computation and communication capabilities for Industry 4.0 and IIoT applications without adding significant power requirements. The research focuses on optimizing energy consumption by taking an overarching view of hardware and software at the system level. In the active state, the IoT-Core can adjust its power consumption at runtime by matching the application demands to the existing energy budget. In sleep state, the module uses a novel Wake-Up Receiver in the 868 MHz frequency band with an average power consumption of 3.5muW, allowing the system to wake up in 32ms. The results are demonstrated on a DC/DC converter, with an efficiency of up to 99.8%, which uses the plug-and-play IoT-Core to become a smart device that can save additional energy when being in idle mode.

This paper proposes a frequency agile fully integrated super-regenerative receiver for spectral power estimation. A 180-nm implementation of the proposed receiver is presented with measurements. The receiver draws 26 μA from a 1.8 Volt supply to scan 60 frequency points between 380 and 960 MHz every 1.8 ms, hence 780 nW per channel. The “resolution bandwidth” lies between 2 and 15 MHz, depending on the quench-signal. No external filter components are used. Filter quality factors greater than 400 are achieved, using an on-chip inductor. The best measured receiver sensitivity is -75 dBm.

Localization capability is a key feature within the developing Internet of Things. This paper proposes an optimal and efficient system solution, based on ultra-low-power wake-up receiver hardware. To that end, a beacon-based quantized-RSSI maximum likelihood approach is employed. Measurements leading to an adapted log-distance path loss model are presented for an exemplary warehouse test environment, forming the basis for the statistical derivations. It is further shown that the hardware-imposed quantization of input power measurements does not significantly impair localization accuracy, while enabling efficient integration of the algorithm. Measurements confirm a mean error of 0.86 meters, with 80 % of distance errors below 1 m.

This paper presents a RSSI-based localisation method for mobile devices and uses the ultra-low power capability of wake-up receivers and its provided RSSI information. Based on measurement results in a test hall, the proposed localisation method was evaluated within real-life radio signal propagation environments at 433 MHz and 868 MHz. The achieved resolution was 1.8 m.

This paper introduces a novel approach for ultra-low-power radio receivers based on Armstrong's super-regenerative architecture. With a power consumption of 1 μW or less the receiver presents a big improvement to the state-of-the-art of 400 μW. In consequence, low maintenance wireless networks are much more feasible. Receiver sensitivity is measured -90 dBm. Spurious emissions from the oscillator are suppressed below -100 dBm, such that the receiver is suitable for wireless sensor networks with high nodal density. Dynamic co-channel interferers are tolerated instantaneously by means of parallel processing and forward error correction.

An ultra-low power wake-up receiver for 2.4-GHz wireless sensor networks, based on a fast sampling method, is presented. A novel multi-branch receiver architecture covers a wide range of interferer scenarios for highly occupied radio channels. The scalability of current consumption versus data rate at a constant sensitivity is another useful feature that fits a multitude of applications, requiring both short reaction times and ultra-low power consumption. The 2.4-GHz OOK receiver comprises a 3-branch analog superheterodyne front-end and six digital 31-bit correlating decoders. It is fabricated in a 130-nm CMOS technology. The current consumption is 2.9 μA at 2.5 V supply voltage and a reaction time of 30 ms. The receiver sensitivity is -80 dBm. Among other sub-100 μW state-of-the-art receivers, the presented implementation shows the best reported sensitivity.

Minimizing waste of resources by reduction of battery replacements in mobile smart objects gives an electronic system a green attribute. Wireless communication is mandatory for modern smart systems. As the receiver's power consumption dominates the total power budget, novel power reduction techniques are recommended. This paper proposes an ultra-low power UHF wake-up receiver IP in a 130 nm CMOS technology. The power consumption is scalable between 3 μW and 28 μW. In contrast to common polling receivers with reaction times of more than 1 second, this novel fully integrated 868 MHz wake-up receiver depicts reaction times between 30 ms and 484 ms. The core size is 1.0 mm 2 . The sensitivity is -83 dBm. Adding such an ultra-low power IP to a SoC circuit, a quick radio interface for remote access on demand is provided and enables a broad variety of innovative applications: remote sensor readout, wireless body area networks, wireless authentification, localisation and asset tracking in logistics and health-care .

This paper describes an innovative approach for integrated ultra-low current wireless receivers for UHF bands in a 180-nm CMOS technology. The classical method of slow periodic switching off of the receiver was picked up, essentially enhanced and applied to a superheterodyne receiver topology. A novel fast sampling pulse operation method for ultra low power integrated receivers is presented meeting both short reaction time and very low power consumption requirements. In addition, the receiver was designed for radio channels with strong interferers. The presented ASIC comprises both an analogue front-end and two digital 31 bit correlating decoders. The current consumption of the fabricated prototype is 2.4 μA at 3 volts supply voltage with a reaction time of 485 ms.

A ultra-low power wake-up receiver based on a novel fast sampling method is presented. The innovative approach allows the scalability of current consumption versus data rate at a constant sensitivity, meeting both short reaction time and ultra-low power consumption requirements. The 868 MHz OOK receiver comprises an analogue superheterodyne front-end and two digital 31 bit correlating decoders. It is fabricated in a 130 nm CMOS technology. The current consumption of the prototype is 1.2 μA at 2.5 volts supply voltage and a reaction time of 484 ms. The receiver sensitivity is -83 dBm thus obtaining a line-of-sight distance of 1200 metres for an assumed transmit power of 10 mW. Compared to other sub-100 μW receivers, the sensitivity of the presented implementation is best.

This paper shows the benefits of a sub-10 muA wake-up receiver circuit used for wireless geofencing and localisation applications with very low maintenance. The wake-up receiver is a wireless receiver which continuously scans the radio channel for certain messages. Having received and decoded such a message containing additional data, the wake-up receiver triggers different actions in smart objects. The wake-up receiver consumes only 7.5 Microwatts and is suitable for mobile battery-operated smart objects. It is shown how the wake-up receiver can be used to implement a wireless indoor geofencing system. This application profits the most from the low and deterministic current consumption and the short reaction time below 500 ms.

This article gives a simple set of rules for the design of integrated inductors with a good quality factor in a standard CMOS process. This guide takes into account almost all the degrees of freedom that a designer has when creating an inductor: the number of sides, the number of metal layers, the center hole, the external radius, metal width and spacing. To verify these rules, a set of inductors for different applications were patterned and measured and quality factors (Q) between 4.6 and 6 were obtained. A 3.8 nH inductor with a Q of 6.1 was manufactured and used in the design of a VCO for a 1.8 GHz application. The design served to test the performance of the VCO and also demonstrated the applicability of the inductors. The measured device phase noise equals –87 dBc per hertz at an offset frequency of 100 kHz.

Different ADC (analog-to-digital converter) algorithms were investigated to find an architecture suited for high speed/high resolution converters based on MESFET technologies. A two-stage cascaded converter was selected for achieving 8-b resolution at a 1-GHz sampling rate. Key components for this kind of converter were developed, fabricated, and characterized. Measurements of the track and hold circuitry showed a droop of 3 mV/ mu s, a slew rate of 3 kV/ mu s, and a setting time of 220 ps. Its accuracy corresponds to 9.5 b at a 1-GHz clock rate with a 100-MHz input frequency. The 4-b quantizer operates up to 1.5 GSps. At 800 MSps, 3.8 effective bits were achieved with input frequencies up to 200 MHz. The digital-to-analog converter necessary to reconstruct the analog signal after coarse quantization was merged into this quantizer to minimize the propagation delay of this path, which determines the maximum sampling rate.< >

A 0.3 /spl mu/m AlGaAs-HEMT technology was used to develop a high speed analog to digital converter (ADC). The 5-b converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independent.<>