In this paper we introduce novel tools for an improved failure analysis process flow for complex packaged microsystems. This failure analysis process flow starts with a non-destructive defect localization using an improved Lock-In Thermography (LIT). After fault isolation, a highly efficient target preparation can be performed using cross-sectioning by combined pulsed-laser ablation and high-current Focused-Ion-Beam (FIB) milling in a specifically modified FIB device. The sample quality achieved is high enough to enable improved high-resolution material analysis of cross-sectioned structures using Scanning Electron Micrography (SEM) and Electron Back-Scatter Diffraction (EBSD), particularly for the analysis of highly resistive bonding interconnects, intermetallic compound identification, and texture analysis. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a microinsert technology is described. The particular benefit of each step is compared to conventional approaches in failure analysis. In addition, the potential of the new failure analysis methodology for future applications using System in Package (SiP) technologies is highlighted.

Failure analysis in complex integrated microelectronic devices is of increasing importance to improve their reliability, quality, and manufacturing yield. Nondestructive testing methods for localisation of shorts and opens in the internal circuitry are required, particularly for complex and fully packaged devices.

A numerical optimisation strategy for interconnections in electronic packaging is demonstrated. The method is based on a toolbox for the parametric generation of finite- element models of package types such as Chip Scale Package (CSP), Micro Lead Package (MLP) or Ball Grid Array (BGA). The novelty of this work is the combination of this modeling toolbox with an optimisation software for automatic parameter variation. Resulting in a convenient tool to investigate the influence of geometry on the relevant quality characteristics of the device. Users can set the parameters to be varied, the ranges of parameter variation and the number of iterations. The optimisation software automatically generates the parameter sets depending on the number of iterations. The generation of a finite-element model for each parameter set, the meshing and the implementation of the required material properties are also automated by the toolbox. Thereafter, the simulation of the desired load conditions results in quality characteristics such as the maximum mechanical stress for each set. After completion of all iterations, the optimisation software provides a user interface for statistical analysis and graphic visualisation of the results. The wirebond geometry is also included in the toolbox. Influence on maximum mechanical stress and fatigue properties under thermal loads is examined during this study. As an example, the effect of the bonding tool geometry on the locations and the value of the maximum mechanical stress in the wirebond material during thermal shocking is determined. This combination of parametric finite-element model generation and automatic parameter variation represents a powerful tool for design automation in packaging technology and product development. The effects of several geometrical parameters on the thermal and mechanical behaviour of packaging interconnects can be predicted. In a virtual product-development process, time- and cost-intensive prototyping and testin- - g can thus be reduced.

An alternative method for exposing IC structures in stacked die packages is described in this paper. Conventional preparation of stacked die packages is complex and time-consuming, requiring costly equipment and experienced operators. This paper presents a method that uses the brittleness of silicon for controlled removal of silicon dies by micro-abrasive blasting. Micro-abrasive blasting affects only the top silicon die; lower dies are protected by the elastic adhesive or the die-attach tape. Dissolving the adhesive layers by chemical wet etching allows step-by-step removal of the stacked die layers. This method is fast and does not require expensive equipment.