Dye penetrant test has been used to detect non hermetic capacitive micromachined ultrasonic transducers (CMUTs). The method has proven its ability to highlight faulty CMUTs membranes among more than hundreds of CMUTs membranes. The fluorescence microscopy image highlights the defective CMUTs with a strong contrast and respecting the shape of the CMUTs, which makes it possible to design robust faulty CMUT automatic identification algorithms. Scanning electron microscopy has been performed in order to check the reliability the detection of the non-hermetic CMUTs. Observations confirmed the reliability of the method.

This paper describes the study carried out in order to characterize the influence of the main fabrication steps of the silicon nano-gauge on their l/f noise. Geometry of the nano-gauge, doping level, thinning process of gauges, doping before or after gauges patterning, release process and treatments for trap curing have been studied. Gauges release has a great impact on the l/f noise: it increases the noise by a factor of up to 100 for the smallest gauges. N2H2 annealing and O 2 plasma treatment reduce the noise generated by the release of the gauge. We assume that the origin behind the noise increase is the trapping-detrapping of carriers in surface traps of the nano-gauge.

This paper reports the conception, the fabrication and the electrical testing of an overdamped silicon accelerometer dedicated to vibrating environments. Squeeze-film damping effects are implemented to drastically reduce the mechanical component bandwidth while keeping a satisfactory resolution. Mechanical filtering of vibrations above 3 Hz is expected to strongly lower the mechanical overcharge and the fatigue of the structure that may occur when the MEMS is exposed to large parasitic vibrations and shocks. Such a low-pass system has not been reported yet, to the best of our knowledge.

We present a novel technique based on an ensemble of Nitrogen-Vacancy (NV) centers of diamond to perform Magnetic Current Imaging (MCI) on an Integrated Circuit (IC). NV centers of diamond permit to measure the three components of the magnetic fields generated by mA range current in an IC structure over a field of 50 x 200 pm with sub-micrometric resolution. Vector measurements allow the use of a more robust algorithm than those used for MCI using GMR or SQUID sensors and it is opening new current reconstruction prospects. Calculated MCI from these measurements shows a very good agreement with theoretical current path. Acquisition time is around 10 s, which is much faster than scanning measurements using Superconducting Quantum Interference Device (SQUID) or Giant Magneto Resistance (GMR). The experimental set-up relies on a standard optical microscope, and the measurements can be performed at room temperature and atmospheric pressure. These early experiences, not optimized for IC, show that NV centers in diamond could become a real alternative for MCI in IC. (C) 2015 Elsevier Ltd. All rights reserved.

Cu-SiO2 direct hybrid bonding is considered as one of the most promising approaches for matching the needs of three dimensional integrated circuits (3D-IC). In this paper we present the results of a complete morphological, electrical and reliability study conducted on four-layer copper structures realized by Cu-SiO2 direct hybrid bonding. Ultra-fine 7 μm pitch, 3 μm × 3 μm pads daisy chains with up to 30 160 connections are bonded with submicron accuracy, matching the interconnection needs in upcoming 3D circuits. A focus is paid on the influence of the temperature of annealing on the bonding quality and electrical performances. Thanks to SEM, FIB/SEM tomography, AFM, TEM and TEM-EDX analysis, the morphology of the bonded structures is described. Electrical parametric tests exhibit very low resistance structures, with high functional yields and low variability. State-of-the-art contact resistivity is obtained for 200 and 400 °C treatments. Unbiased HAST, temperature cycling and temperature storage tests demonstrate excellent reliability performances. Finally, an electromigration resistance comparative study is conducted on bonded copper lines with TaN/Ta and TiN diffusion barriers.

Failure analyses on μinsert technology used for 2.5D stacking are carried out after 1000 hours of damp heat test on nickel, copper and gold-nickel μinserts. We show that nickel μinserts are prone to delamination when the force applied on the reported die during bonding process is not homogeneous or lower than an optimal value. After the test, one out of eight tested gold-nickel μinserts is subject to a failure induced by gold-aluminum intermetallic compound growth. These intermetallic compounds engender Kirkendall voids which cause a steady increase of a few tens of percents of the electrical resistance of the gold-nickel μinserts. Failures of copper μinserts are due to residues of the titanium used to protect the copper seed layer before the electroplating step. An improper assembly seems to be the cause of failure in each case and it is easily detectable after the bonding process by measuring the electrical resistance of μinserts.

Micro-insert technology is a wafer level stacking technology offering main advantages such as simplicity, low cost and compatibility with chip assembly technologies. This paper presents recent preliminary reliability tests results. Thermal cycling tests between -40°C and 125°C and damp heat tests at 85%RH/85°C are performed, tests results show that micro-insert technology is very robust. A interesting correlation is found between initial interconnection electrical resistance and time to failure during damp heat test, allowing die sorting for reliability.

In this work, spots of charges have been injected on typical silicon nitride used for RF-MEMS switches. Several relative humidity (RH) conditions have been used for the charge injections. The evolution of these spots with time has been assessed thanks to electrostatic force microscopy (EFM) measurements. Experimental results confirm the hypothesis of surface conduction enhancement but also show a 30% increase of the density of injected charge by humidity. It has been also shown that a level of 40% RH decreases the charge relaxation time by a factor 10 to more than 100 compared to a charge relaxation process occurring under dry atmosphere. This phenomenon may be due to the ability of protons contained in the water to diffuse trough silicon nitride.

In this paper we introduce novel tools for an improved failure analysis process flow for complex packaged microsystems. This failure analysis process flow starts with a non-destructive defect localization using an improved Lock-In Thermography (LIT). After fault isolation, a highly efficient target preparation can be performed using cross-sectioning by combined pulsed-laser ablation and high-current Focused-Ion-Beam (FIB) milling in a specifically modified FIB device. The sample quality achieved is high enough to enable improved high-resolution material analysis of cross-sectioned structures using Scanning Electron Micrography (SEM) and Electron Back-Scatter Diffraction (EBSD), particularly for the analysis of highly resistive bonding interconnects, intermetallic compound identification, and texture analysis. To illustrate the complete workflow of the approach, a failure analysis of a vertically integrated microsystem using a microinsert technology is described. The particular benefit of each step is compared to conventional approaches in failure analysis. In addition, the potential of the new failure analysis methodology for future applications using System in Package (SiP) technologies is highlighted.

In this paper we introduce an original Electrostatic Force Microscopy (EFM) -based methodology which allows a rapid and easy calculation of the charge density value of electric charges injected in a silicon nitride dielectric layer for conditions which prevail during MEMS switch actuation. The calculation of the number of trapped charges is reproducible and in agreement with the results already published in the literature. A physical model is suggested which describes the charge spot behavior inside the silicon nitride. This model can explain the pull-in voltage shift due to dielectric charging in a RF-switch MEMS.

In many complex systems under development, the cost of integration and the compromises in performance that can result from the integration process can become prohibitive. Therefore, the establishment of a technology which enables the system level integration of devices from different technological families at the package level can become very attractive. In particular, since each component can be built in its optimum technology flow and interconnections within the package tend to be very short, very high performance can be achieved. The work to be presented in this paper describes direct and electrical reliability measurements of test structures used to optimise the electrical performance of micro insert based interconnection system as a function of flip chip mounting parameters. Micro-inserts have a great deal of potential for the face to face interconnection of stacked systems in three-dimensional integration technologies.

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems; it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. SimCard Prototypes have been developed and evaluated in usual and moisture conditions.Thermal cycling of test structures between -40°C and + 85°C has been performed at wafer level and results indicate that the average resistance of the daisy chain observed between the two devices does not change. However, electrical yield of the structures under damping tests @85°C and 85% of humidity decrease significantly as a consequence of the glue degradation. However further damping tests have been realized on the final packaged cards without any deterioration of the prototype.

In this paper a test structure is described which facilitates the evaluation of interconnection schemes for chip on wafer attachment and interconnection. Microinsert technology is described and some of the characterization that the test structure permits is discussed. Thermal cycling experiments were performed on this test structure and although the resistance of the contact chain seemed not to change as a function of number of cycles, detailed investigation revealed that the metal resistance was reducing while contact resistance was increasing and the two effects were trading off against each other. Possible explanations for this behavior have been provided.

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems, it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. Thermal cycling of wafers between -40degC and + 85degC has been performed at wafer level and results indicate that the average resistance of the daisy chain observed between the two devices does not change significantly. However, the standard deviation of the distribution increases slightly as a consequence of thermal cycling. Analysis of interconnect and contact resistance indicates that while metal interconnect resistance diminishes, possibly as a function of annealing effects and grain growth. The resistance of individual contacts between devices is increasing somewhat. These two phenomena are considered to be effectively canceling each other out to provide the macroscopic behavior reported above. An average contact resistance of 14 mOmega was observed in devices which had undergone almost 500 cycles (an increase of ~6 mOmega from the starting resistance.

Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems, it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. Detailed electrical characterization of the technology has been benchmarked against acoustic microscopy and close correlations have been identified using a combination of these techniques. Process constraints identified in the course of this work have been identified and used in the optimization of the technology.

The many advantages of optical fibers for their use in various nuclear environments ushered the respective communities to extensive studies over the last decades. Forecasting the behavior of fiber-optic links exposed to ionizing radiation still remains an important issue. We have developed an industry-aimed pragmatic method based on a simple model for the prediction of radiation induced losses in commercially available optical fibers exposed to Co-60 gamma rays. When environmental and measurement conditions are well defined, long-term losses could be predicted with a precision of about 15%, for dose rates ranging between 100 Gy/h and 3 kGy/h and total doses up to MGy levels. Thermally induced effects were also considered, between ambient temperature and 80 degreesC. From an interpretation of these results, we discuss its applicability and potential further improvements.

We have developed an industry-aimed pragmatic method based on a known model for the prediction of radiation induced losses in single mode optical fibers exposed to /sup 60/Co gamma rays. When environmental and measurement conditions are well defined, long-term losses could be predicted with a precision of about 15%, provided a sufficiently large data-set is available. From an interpretation of these results, we discuss its applicability and potential further improvements.