Benefiting from considerable progress in the design of low-power, low cost and high-speed millimeter-wave circuits, Polymer Microwave Fibers (PMF) are gaining interest in the context of serial links. In this work, an innovative dual-band Quadrature Phase Shift Keying (QPSK) architecture, which is based on integrated wideband and low loss differential hybrid couplers, is proposed to increase data rate capability while still preserving low power and moderate range potentials. A circuit demonstrator in 28 nm CMOS FD-SOI is presented to validate the concepts. It achieves fifth harmonic locking on a wide continuous locking range and realizes 9 Gb/s data rate in the E-band.

As millimeter-wave applications mostly rely on differential topologies, a differential design for quadrature hybrid coupler is also desired. The proposed Differential Vertical Hybrid Coupler (DVHC) concept is presented and dimensions are given for a 75 GHz operating frequency using 28 nm CMOS FDSOI technology. Simulated insertion loss is only 0.5 dB while return loss and isolation are close to 30 dB exhibiting very weak frequency dependence on all ports. Measurements on test structures confirm wideband operation and low insertion loss. Additionally, a flip-chip compatible RF pad with ultra-low parasitic capacitance is designed here and characterized (11 fF reported at 75 GHz).

In this paper, a 64QAM and OFDM capable CMOS transceiver designed for wireless communications in the 60 GHz band is used in combination of a plastic waveguide to realize a 4m link. The plastic waveguide is made of Teflon (PFTE) and features an innovative design enhancing confinement and propagation robustness compared to literature. The first QPSK communication over plastic waveguide is then demonstrated at a rate of 4 Gb/s. It was even possible to perform 64QAM (12 Gb/s) by using scope direct demodulation instead of the receiver chip. Preliminary results also indicate that OFDM communication is possible as well, further highlighting the versatility of plastic waveguides and paving the way to reconfigurable wireless / wireline use cases.

As applications in E-band (60–90 GHz) are gaining increasing commercial interest, a full-band, low-cost and high performance microstrip to rectangular waveguide standard (WR12) transition is desired. The presented design covers a bandwidth from 55 GHz to 95 GHz thanks to smooth impedance transitions. A dielectric tip is machined at the end of the microstrip line to couple with a double ridged waveguide section, which is then linearly tapered to a standard WR12 section. Measurements on back-to-back transitions confirm wideband operation beyond E-band with a 3.6 dB average insertion loss (1.8 dB per transition) and return loss lower than 10 dB in the 55 to 95 GHz frequency range. Additionally, group delay is measured showing broadband operation in line with the simulation.

Alors que l’interet commercial pour les applications en bande E (60 - 90 GHz) grandit, le besoin d’une transition haute performance et faible cout entre une ligne micro-ruban et un guide d’ondes standard (WR12) se fait sentir. La geometrie presentee ici couvre une bande passante allant de 55 a 95 GHz grâce a une pointe dielectrique et a une section a double moulure debouchant progressivement sur une section WR12 standard. Les mesures effectuees sur deux transitions dos-a-dos montrent des pertes d’insertion moyennes de 3,6 dB et des pertes de reflexion superieures a 10 dB. De plus, des mesures de temps de propagation de groupe confirment le fonctionnement large bande de la transition, en accord avec les resultats de simulation.

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm(2), or 0.23 mm(2) when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, - 10 dBm of IIP3 and more than 32 dB of image rejection.

The aim of the 2.4GHz front-end receiver presented in this paper is the minimization of both cost and energy consumption, focusing on WPAN IEEE 802.15.4 transceivers. It includes the entire RF part, from the balun to the first stage of the channel filter, as well as the LO signal conditioning cells. The proposed architecture uses an unmatched inductorless LNA and a new clocking scheme on a standard passive mixer. Compared to previously reported IEEE 802.15.4 receivers, an area reduction by at least 70% is achieved. The power consumption is relatively low at 5.4mW with a state-of-the-art noise and linearity performance. The receiver front-end operates at 1.35V. It is implemented in a 90nm CMOS technology using two thick metals, and alucap with RFMOM capacitors.