Unlike MOSFET technology, Field-Coupled Nanocomputing (FCN) structures are based upon a completely new computational paradigm. The basic computational element propagates the information through near-field interaction with neighboring elements. The potential of this principle is really promising because of the absence of current flow, leading to low power consumption. Here, we explore the in-plane NanoMagnetic Logic implementation. The analysis of complex circuits highlights the limitations due to their planar structure: mixing logic and interconnections on a single layer leads to an explosion of the circuit area. In this paper, we evaluate whether a 3D implementation of the structure can abruptly reduce the major limitation of the technology. We propose a solution by using a particular clock delivery method, named Virtual Clock. The analysis is carried out through micromagnetic and functional simulations on medium complexity architectures. The results obtained clearly highlight a large improvement in circuit area and power consumption.

In this paper we present a tool, NANOcom, specifically developed for the bottom-up design and formalization of electronic circuits with a regular, matrix-like, structure. NANOcom allows to easily describe any kind of circuits and technologies where neighboring logic elements are dynamically coupled. Logic elements and interconnections are placed on a three-dimensional grid. Each element is characterized with an RTL model that describes its logic behavior and how it communicates with neighboring elements. Starting from the grid layout and the model, NANOcom automatically creates a VHDL code describing the whole structure. NANOcom can be used to simulate both standard CMOS circuits, such as PLAs, and new emerging technologies, like NASICs (Nanoscale Application Specific Integrated Circuits), memristor-based circuits and field coupled technologies, such as Nanomagnet Logic (NML), Quantum dot Cellular Automata (QCA) and Molecular QCA.

Emerging technologies are gaining an increasing attention due to the slowdown of CMOS development. NanoMagnet Logic (NML), among emerging technologies, increases the potentials for developing fully magnetic circuits. Using a magnet as a building block for logic circuits has the advantage to merge logic and memory in the same device. Moreover, circuits have low dynamic and no stand-by power consumption. Even though demonstrations exist for small circuits, the experimental feasibility of complex NML circuits still represents a critical point for this technology. In this paper, we outline the possibility to design NML circuits based on the technological structure of magnetic RAMs (MRAMs). NML circuits based on MRAMs rely on a well-developed technology that provides a natural interface with CMOS world. To study this new NML implementation a novel tool, NANOcom, was developed to easily design complex circuits. Simulations were then performed using an high-level behavioral model described using VHDL language. Two types of circuit layouts, based on different technological constraints, are investigated. To evaluate the performance of this new NML implementation, a 4-bit Galois multiplier is used as a testbench. The Galois multiplier is the basic block of cryptographic circuits, an ideal target for this technology. Results obtained are encouraging and can unlock interesting options for the future development of NML technology.

Cryptography provides techniques to cypher and de-cypher sensitive information through a token called key in order to store and transmit it across insecure networks. The goal of cryptography is to protect information from potential attackers and to enable access to authorized users only. Several hardware cryptographic devices are entering the market. However, these devices can be subject to passive attacks that consist in retrieving secret data by observing the side-channel behaviour of the device (i.e. execution time, power consumption, electromagnetic field). This work studies the robustness of SEcube™, an innovative secure hardware product against Differential Power Analysis attacks. SEcube™ is a system-on-chip equipped with three devices interconnected and embedded in a single chip: an ARM Cortex M4 low-power processor, a Lattice MachXO2-7000 FPGA and a SmartCard SLJ52G (EAL5+ certified). Moreover, in order to examine the security enhancement of this platform, we perform the same analysis with a similar board equipped with the same microprocessor and then compare the results. Experimental results show that the number of correct bits is similar between the two platform.

With the advancement of fabrication processes, bistable single domain nanomagnets are being exploited to design digital logic circuits. The fabricated circuits are however particularly sensitive to process variations and thermal noise.In this paper we exploit these weaknesses to design a true random number generator. The underlying idea is that the nanomagnet can be forced in a metastable state by using an external magnetic field. The removal of the field will lead the nanomagnet to a random state. To validate the proposed structure we use micromagnetic simulations considering both process variations and thermal noise. We present here our preliminary and very promising results.

With the advancement of fabrication processes, single domain nanomagnets devices are being exploited to design digital logic circuits. In this work we evaluate the exploitability of nanomagnetic technologies to design cryptographic devices, such as True Random Number Generators and Physical Unclonable Functions. To quantify the source randomness we use the tests defined in NIST SP 800-22 [1] while for simulate the electronic devices we use micromagnetic simulations and Digital Signal Processing to reproduce circuit binary response.

NanoMagnet Logic (NML) is an emerging technology that allows to design digital circuits using nanomagnets. Each magnet has only two possible states and encodes digital information without the need for currents or voltages. This behavior differentiates NML circuits from charge based technologies. The advantages provided by NML circuits are a possible very low power consumption, and the ability to mix logic and memory in the same device. While a rich experimental activity on NML circuits can be found in literature, the feasibility of a complete NML system remains to be demonstrated yet. In this work we explore the possibility of implementing NML logic circuits based on the physical structure of Magnetic RAM (M-RAM). The advantages are twofold: First, M-RAM is a well developed technology, ready for the commercial stage, second it intrinsically provides an interface toward the CMOS world. To demonstrate the feasibility of NML circuits based on M-RAM we have designed a 3-input Ex-OR gate, using two different physical layouts for control signals. The first solution is strictly based on the M-RAM structure; the second solution requires a more complex fabrication process but leads to a smaller area. Circuits are simulated using VHDL language, with the aid of a tool that we have developed which automatically generates the VHDL code starting from the circuit layout. Overall, the solution here presented is a considerable step-forward toward the development of a complete magnetic circuit.

Secure implementations have two primary goals: being optimized (with respect to area, latency, power, or throughput) and secure against physical attacks, such as side channel analysis. Composite fields have been often proposed as a solution for the former problem, allowing implementations of the Advanced Encryption Standard targeted at resource constrained applications: additionally, they may also be a countermeasure against passive analysis and make an attack more difficult. In this paper, we present an AES design fully implemented on composite fields and evaluate its robustness against Differential Power Analysis.

Nano-Magnetic Logic (NML) is a promising candidate to substitute CMOS technology since it is characterized by very low power consumption and it can combine computation and memory in the same device. Several works analyze this technology at device level; nevertheless a higher level analysis is required to fully understand its potentials. It is actually fundamental to analyze how an architecture of realistic complexity can be really implemented taking into account the physical limits due to technology, and which performance it could consequently reach. We present here a physical design and test methodology based on our tool ToPoliNano, which allows analyzing circuits using models specifically targeted for this technology. We developed an automatic engine for placing and routing combinational NML circuits including as constraints realistic rules due to currently available fabrication processes. After the place and route phase, ToPoliNano also allows to perform a circuit logical simulation, detailed at the single nanomagnet level. Furthermore this tool has the ability to analyze and test circuits based on NML, considering the impact that process variations and faults have on the logical behavior of the circuit.