Hearing research and audio technology have met to cope with hearing impairment issues under multiple aspects.Among them, spatial sound reproduction systems have been used for both clinical and research purposes to optimize signal processing algorithms of Hearing Aids (HAs) and for the assessment of hearing loss under complex acoustic conditions.Furthermore, spatial sound reproduction systems are also well suited for the administration of listening tests properly designed to optimize HAs fittings, for which ecological validity is crucial to achieve effective hearing improvement in daily life.Based on well-grounded 3D sound systems, this work discusses the procedure of installation, signal network set-up and evaluation of a costeffective Virtual Sound Environment (VSE) reproduction system that is meant to be replicated and used indoors in small settings for clinical purposes.The system, aimed at reproducing sound fields starting from 3 rd -order ambisonics encodings, is based on a spherical array of 16 commercial 2-way active loudspeakers installed inside of a small acoustically dampened room of 35.5 m 3 .Results of this work can be summarized as follows: (i) a small spatial sound reproduction system was tuned and (ii) a preliminary investigation of the accuracy of the reproduced VSEs compared to the real environments was performed.

Recent research has focused on the validation of methods and procedures to perform ecological tests for the assessment of hearing sensitivity under the complex acoustical conditions of everyday life environments.Virtual Reality (VR) has been extensively used to reproduce immersive acoustical scenes in combination with visual cues in order to account for the multisensory perception of the physical environment that happens in real-life situations.However, due to the complexity of recording and reproduction procedures, the main studies focus on either audiovisual rendering of simulated scenarios or in-field audio recordings without real visual contextualization.This work proposes a pilot case study involving a challenging listening environment (a conference hall with 3.2 s of reverberation time at mid-frequencies), where 360° audiovisual scenes were recorded and then reproduced in laboratory using a 16-loudspeakers array and a VR headset.Multiple scenarios involving different target-and noisesource positions were acquired through 3rd-orderambisonics recordings of room impulse responses and 360° stereoscopic video footage.Speech intelligibility tests were auralized for these scenarios, considering informational masking noise at different signal-to-noise ratios, and

Honeybees are one of the most important pollinators in nature for both crop production and biodiversity preservation.The increase in bee mortality observed in the last decade motivated the development of continuous monitoring systems to better understand this phenomenon.Different solutions have been presented in the literature, and particularly sound analysis appears the most promising among the non-invasive techniques.In this context, we developed a machine learning framework for the analysis of the sound produced by bees for the detection of the queen bee's presence.The presence of the queen is an important indicator of the colony's health.In this work, we investigated Short Time Fourier Transform and Mel Frequency Cepstral Coefficient audio features with support vector machines and neural network classifiers.The results indicate the potential of machine learning methods for supporting the researchers' study and beekeepers in managing such important insects.

This study aims to estimate the number of people in a canteen from the babble noise level in the room.Noise levels were measured in the CIRCOOP canteen of the Politecnico di Torino across 4 days during the COVID pandemic, while three people counters, based on IR sensors, were located at the entrance and at the exit of the canteen.Reverberation time was also measured to calibrate the acoustic model in Odeon 16 and Grasshopper application of Rhinoceros 7 was used to calculate some parameters needed for the application of two prediction algorithms.The former assumes a diffuse field while the latter does not, and instead, it considers the rate of spatial decay per distance doubling and the interpersonal distance.Besides the acoustical parameters of the room, the models need as input the group size g and the Lombard slope c, which strongly depend on human context.In the case of this canteen, the best matching was obtained with g=8 and c=0.5 for both the models.Our results showed that the prediction of the number of people from the babble noise is possible only for noise levels lower than 70 dB(A).

Magnonics addresses the physical properties of spin waves and utilizes them for data processing. Scalability down to atomic dimensions, operation in the GHz-to-THz frequency range, utilization of nonlinear and nonreciprocal phenomena, and compatibility with CMOS are just a few of many advantages offered by magnons. Although magnonics is still primarily positioned in the academic domain, the scientific and technological challenges of the field are being extensively investigated, and many proof-of-concept prototypes have already been realized in laboratories. This roadmap is a product of the collective work of many authors, which covers versatile spin-wave computing approaches, conceptual building blocks, and underlying physical phenomena. In particular, the roadmap discusses the computation operations with the Boolean digital data, unconventional approaches, such as neuromorphic computing, and the progress toward magnon-based quantum computing. This article is organized as a collection of sub-sections grouped into seven large thematic sections. Each sub-section is prepared by one or a group of authors and concludes with a brief description of current challenges and the outlook of further development for each research direction.

The requirement of high memory bandwidth for next-generation computing systems moved the attention to the development of devices that can combine storage and logic capabilities. Domain wall-based spintronic devices intrinsically combine both these requirements making them suitable both for non-volatile storage and computation. Co\Pt and Co\Ni were the technology drivers of perpendicular Nano Magnetic Logic devices (pNML), but for power constraints and depinning fields, novel CoFeB\MgO layers appear more promising. In this paper, we investigate the Ta2\CoFeB1\MgO2\Ta3 stack at the simulation and experimental level, to show its potential for the next generation of magnetic logic devices. The micromagnetic simulations are used to support the experiments. We focus, first, at the experimental level measuring the switching field distribution of patterned magnetic islands, Ms via VSM and the domain wall speed on magnetic nanowires. Then, at the simulation level, we focus on the magnetostatic analysis of magnetic islands quantifying the stray field that can be achieved with different layout topologies. Our results show that the achieved coupling is strong enough to realize logic computation with magnetic islands, moving a step forward in the direction of low power perpendicularly magnetized logic devices.

Unlike MOSFET technology, Field-Coupled Nanocomputing (FCN) structures are based upon a completely new computational paradigm. The basic computational element propagates the information through near-field interaction with neighboring elements. The potential of this principle is really promising because of the absence of current flow, leading to low power consumption. Here, we explore the in-plane NanoMagnetic Logic implementation. The analysis of complex circuits highlights the limitations due to their planar structure: mixing logic and interconnections on a single layer leads to an explosion of the circuit area. In this paper, we evaluate whether a 3D implementation of the structure can abruptly reduce the major limitation of the technology. We propose a solution by using a particular clock delivery method, named Virtual Clock. The analysis is carried out through micromagnetic and functional simulations on medium complexity architectures. The results obtained clearly highlight a large improvement in circuit area and power consumption.

Nanocomputation based on emerging devices is becoming a major subject of study as a possible alternative to CMOS. These new technologies are highly defective due to the immaturity of the processes. It is extremely important then for both the technologists and the application engineers to have feedbacks on the impact on the circuit of such defectivity. The current scenario, though, evidences a complete lack of algorithms and tools for analyzing these kinds of circuits fault tolerance as well as for designing defect-tolerant circuits. This paper presents an unprecedented CAD ensemble. I) FaTToR, an algorithm for optimizing nanoarray-based circuits tolerance to defects. II) ToPoliNano based on a multithreading Monte Carlo switch-level simulation engine, a CAD for thoroughly analyzing the circuit defect tolerance against defect distributions derived by fabrication processes. Results are demonstrated in terms of output error rate and yield for nanoarray-based circuits of medium complexity. Several defect distributions are used as inputs for both FaTToR optimization and ToPoliNano validation. Our contributions represent a fundamental step forward both in terms of design automation methodology and in terms of specific feedbacks on the technology here studied. The approach is general and can be adopted to several other emerging technologies based on regular fabrics

Perpendicular NanoMagnet Logic (pNML) can be considered one of the most interesting emerging technology since it has unique features that cannot be naturally implemented with standard transistor technologies. Each device can act both as a memory and a logic circuit. Because of its intrinsic properties, this technology makes it possible to easily design 3D circuits. In this paper, we propose several complex architectures by exploiting the 3D integrability of the pNML technology. The presented circuits belong to different categories, covering both combinational and sequential circuits. Memory elements and logic circuits have been designed and simulated taking into account the technology constraints. As an absolute novelty, the first Finite State Machine based on pNML is also introduced.

Emerging technologies, such as field-coupled devices, are being studied in order to integrate or partially replace CMOS technology in digital electronics. These emerging technologies rely on completely different paradigms. In this work, we propose an approach to compare circuit based on two implementations of the Nano Magnet Logic that can be extended to other emerging devices. As case study, the architecture of a 2-to-l multiplexer and a carry select adder are considered. Their performance is investigated by means of MagCAD, a powerful graphical layout tool, used to simplify the process and speed up this analysis.

Among emerging technologies, perpendicular Nanomagnetic Logic (pNML) seems to be very promising because of its capability of combining logic and memory onto the same device, scalability, 3D-integration and low power consumption. Recently, Full Adder (FA) structures clocked by a global magnetic field have been experimentally demonstrated and detailed characterizations of the switching process governing the domain wall (DW) nucleation probability Pnuc and time tnuc have been performed. However, the design of pNML architectures represent a crucial point in the study of this technology; this can have a remarkable impact on the reliability of pNML structures. Here, we present a compact model developed in VHDL which enables to simulate complex pNML architectures while keeping into account critical physical parameters. Therefore, such parameters have been extracted from the experiments, fitted by the corresponding physical equations and encapsulated into the proposed model. Within this, magnetic structures are decomposed into a few basic elements (nucleation centers, nanowires, inverters etc.) represented by the according physical description. To validate the model, we redesigned a FA and compared our simulation results to the experiment. With this compact model of pNML devices we have envisioned a new methodology which makes it possible to simulate and test the physical behavior of complex architectures with very low computational costs.

In nano magnetic logic (NML), single-domain nanomagnets enable logic operations. Binary information can be encoded thanks to its bistable magnetization. Many implementations are currently discussed in literature, among them one promising candidate is perpendicular-nano magnetic logic (pNML). It features several advantages like the controllability of the switching mechanism, the simplicity of design, and the natural predisposition of being integrated in three-dimensional (3-D) architectures. Here we show how this technology can be adopted in the design of 3-D logic architectures. Physical equations and quantities have been gathered from experimental demonstrations of pNML devices; formulas have then been fitted and implemented in VHDL (VHSIC Hardware Description Language). In this paper, we present an analysis of pNML circuits: initially a Multiplexer has been manufactured and characterized, then our compact model has been tested through simulations. Moreover, the MUX has adopted to design a generic n-bit accumulator. Our results demonstrate that the compact model makes it possible to perform fast simulations, while maintaining a fine level of accuracy. Thanks to its flexibility, novel materials, geometric variations, and other technological improvements can be easily integrated in order to be tested at circuit level. We anticipate our essay to be a starting point for the exploration of large 3-D digital circuits.

SummaryThe increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic.The methodology is based on three main steps: (i) we performed exhaustive physical‐level simulations of basic blocks based on a detailed finite‐element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano, we simulated using fanomag, now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on.The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.

In most computational systems memory access represents a relevant bottleneck for circuits performance. The execution speed of algorithms is severely limited by memory access time. An emerging technology like Nano Magnet Logic (NML), where its magnetic nature leads to an intrinsic memory ability, represents therefore a very promising opportunity to solve this issue. Nano Magnet Logic is the ideal candidate to implement the so called Logic-In-Memory (LIM) architecture. But how is it possible to organize an architecture where logic and memory are mixed and not separated entities? In this paper we try to address this issue presenting our recent developments on LIM architectures. We originally conceived a LIM architecture without considering any technological constraints. Here we present the first adaptation of that architecture to Nano Magnet Logic technology. The architecture is based on an array of identical cells developed on three virtual layers, one for logic, one for memory and one for information routing. These three virtual layers are mapped on two physical layers exploiting all our recent improvements on Nano Magnet Logic technology, which are validated with the help of low level simulations. The structure has been tested implementing two different algorithms, a sort algorithm and an image manipulation algorithm. A complete characterization in terms of area and power is reported. The structure here presented is therefore the first step of an ongoing effort directed toward the development of truly innovative architectures.

The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck in data exchange between memory and processor.We envisage a revolutionary path for the future relation between memory and logic in parallel processors, where a new type of architecture exploits the principle of caching to the limit. Our Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel solutions. The architecture we propose, here in its preliminary version, has an array organization and each element in the array is based on three blocks: a logic unit for processing, a smart memory block and a routing structure for inter block communication. In this article we show the benefits of this approach with an application example in the image processing field. We can achieve a 4X computational time reduction for an image processing algorithm (Summed Area Table) with respect to the best architecture present in the literature, even with a preliminary and not optimized version.Besides the adoption of massive parallelism to increase performance, new technologies to open the post-CMOS era are explored. Among them NanoMagnet Logic (NML) is particularly interesting for its ability to mix logic and memory in the same device. We present here the preliminary results of the NML implementation of the LIM architecture. We thus demonstrate that it is not only a good solution for a standard CMOS technology but can also exploit the potential of an emerging technology as NML.

One of the most innovative solutions studied as an alternative technology to CMOS transistors is represented by NanoMagnetic Logic (NML). It exhibits remarkable characteristics that overcome some intrinsic limitations of CMOS as low power consumption and the possibility to merge logic and memory in the same device. We present the design of a full adder entirely based on single domain out-of-plane nanomagnetic logic (pNML). We propose different solutions of the same circuit which allow us to obtain the best performance in terms of occupied area and timing. We modeled, using VHDL (VHSIC Hardware Description Language), the pNML basic elements and then we performed micromagnetic simulations to demonstrate the correct operation of the circuits.

We automatically maximize fault-tolerance in nanoarrays based on silicon nanowires and Gate-All-Around transistors optimizing their topology vs. several distributions of faults inherited by technology. We added a Monte Carlo engine in our nanoarchitecture design tool ToPoliNano and verified the effectiveness of the fault-tolerance algorithm over several circuits and faults distributions.

Nano-Magnetic Logic (NML) is a promising candidate to substitute CMOS technology since it is characterized by very low power consumption and it can combine computation and memory in the same device. Several works analyze this technology at device level; nevertheless a higher level analysis is required to fully understand its potentials. It is actually fundamental to analyze how an architecture of realistic complexity can be really implemented taking into account the physical limits due to technology, and which performance it could consequently reach. We present here a physical design and test methodology based on our tool ToPoliNano, which allows analyzing circuits using models specifically targeted for this technology. We developed an automatic engine for placing and routing combinational NML circuits including as constraints realistic rules due to currently available fabrication processes. After the place and route phase, ToPoliNano also allows to perform a circuit logical simulation, detailed at the single nanomagnet level. Furthermore this tool has the ability to analyze and test circuits based on NML, considering the impact that process variations and faults have on the logical behavior of the circuit.

In order to assure the best learning experience, the teaching activity in Electronic Engineering is expected to closely follow the rapid evolution of CMOS technology. As a consequence the necessity of new teaching tools arises. These instruments must be flexible enough not only to follow technology evolution, but also to improve the learning experience by assuring interactivity and adaptability. In this work we present a tool “made by students for other students” which analyzes and compares different technologies from nanoscale CMOS transistors to emerging technologies, based for example on Carbon Nanotubes and Silicon Nanowires. The aim of this tool is to grant the students, but also the designers, with a useful instrument to understand the impact of scaling and of emerging technologies on nanoelectronics circuits. It allows the evaluation of different circuit parameters, from device level (currents, capacitances, ...) to system level (power, speed, area, ...). Since the best way to learn is “learning by doing”, the tool, based on the open source software GNU Octave, has a modular structure. In this way students not only can use it, but they can develop new modules starting from the literature, from teacher's experiences or from interesting case studies, contributing themselves to improve the learning experience of other students.

In Nano Magnetic Logic (NML), single-domain nanomagnets enable logic operations. Binary information can be encoded thanks to its bistable magnetization. Many implementations are currently discussed in literature, among them one promising candidate is perpendicular-Nano Magnetic Logic (pNML). It features several advantages like the controllability of the switching mechanism, the simplicity of design and the natural predisposition of being integrated in 3D architectures. Here we show how this technology can be adopted in the design of 3D logic architectures. Physical equations and quantities have been gathered from experimental demonstrations of pNML devices; formulas have then been fitted and implemented in VHDL (VHSIC Hardware Description Language). In this paper we present an analysis of pNML circuits: initially a Multiplexer has been manufactured and characterized, then our compact model has been tested through simulations. Moreover, the MUX has adopted to design a generic n-bit accumulator. Our results demonstrate that the compact model makes it possible to perform fast simulations, while maintaining a fine level of accuracy. Thanks to its flexibility, novel materials, geometric variations and other technological improvements can be easily integrated in order to be tested at circuit level. We anticipate our essay to be a starting point for the exploration of large 3D digital circuits.