This paper investigates the use of Neural Network (NN) nonlinear modelling for Power Amplifier (PA) linearization in the Walsh-Hadamard transceiver architecture. This novel architecture has recently been proposed for ultra-high bandwidth systems to reduce the transceiver power consumption by extensive parallelization of the digital baseband hardware. The parallelization is achieved by replacing two-dimensional quadrature modulation with multi-dimensional Walsh-Hadamard modulation. The open research question for this architecture is whether conventional baseband signal processing algorithms can be similarly parallelized while retaining their performance. A key baseband algorithm, digital predistortion using NN models for PA linearization, will be adapted to the parallel Walsh architecture. A straighforward parallelization of the state-of-the-art NN architecture is extended with a cross-domain Knowledge Distillation pre-training method to achieve linearization performance on par with the quadrature implementation. This result paves the way for the entire baseband processing chain to be adapted into ultra-high bandwidth, low-power Walsh transceivers.

Exploring millimeter-wave bands presents fresh opportunities for new high data rates communication standards, yet confronts technological challenges like power amplification. Digital predistortion (DPD) offers a solution to enhance the linearity of the amplification while keeping high efficiency. Since Envelope Transient simulations (ET) are time-consuming during circuit design, designers often restort to experimental DPD verification instead. This paper proposes two co-simulation workflows to simulate modulated signals on Integrated Circuits (IC) Power Amplifiers (PA) with an application of DPD. Simulation results indicate that the computational modeling of power amplifiers enables 99% faster schematic and post-layout (PLS) ET simulations, reducing the time needed from months to minutes while maintaining comparable output accuracy.

A Proof-of-Concept (PoC) of a wideband Power Amplifier (PA) with controlled efficiency based on second har-monic matching is proposed in this paper. The context of carrier aggregation in the 5G standard needs wide operating bandwidth with high Power Added Efficiency (PAE). Thus, the output network uses harmonic processing techniques to control the PAE over the bandwidth (BW) from 0.65 to 1.5GHz. The gain is between 9.2 and 12.2dB, $P_{sat}$ is between 24.2 and 27.2 dBm, and the $\text{PAE}_{\max}$ is between 42.5 % and 57 % with a best improvement of 16 points at 1.4GHz.

Millimeter-wave hands open new bands of interest for ultra-high-speed wireless communications, but face technological bottlenecks such as power amplification. Working near the maximum oscillation frequency of the transistor leads to low intrinsic gain and low efficiency. Digital predistortion (DPD) achieves a higher power efficiency without degrading linearity. This paper presents a co-simulation workflow to design jointly DPD and the power amplifier (PA) in order to reach the optimum performances in linearity and power-added efficiency (PAE). The design of a PA at a center frequency of 142 GIIs using the CMOS 28nm FDS01 technology from S'IMicroelectronics demonstrates how the design flow can take into account continuous wave (CW) and modulated signal simulations with and without DPD. The linearity performance is highlighted on the adjacent channel power ratio (ACPR) with an improvement of 4dB on an OFDM signal with 800 MHz bandwidth.

This paper presents a low-cost bench to provide a comprehensive set of measurement capabilities to train students in RF Integrated Circuits characterization and their enhancement with a focus on Power Amplifier (PA) and its associated Digital Predistortion (DPD). It brings into play two Universal Software Radio Peripherals (USRP) and a user-friendly interface to perform measurements on a radio-frequency (RF) chain and to extract circuit characteristics. The interface was designed on MATLAB App Designer to provide students with an ergonomic and pedagogical user experience. Additionally, DPD software was designed for students to evaluate various PA linearization models and benchmark their performances. Furthermore, students can use this bench to test and validate their own circuit designs, providing hands-on experience and helping them to gain a better understanding of the principles of RF design. Finally, a survey displays feedback on students’ pedagogical appreciation of the bench.

A novel non-linear adaptive filter for the linearization of Radio Frequency (RF) Power Amplifiers (PAs) is presented. In this study, we aim at reducing the Digital Predistortion (DPD) complexity and enhancing its convergence speed for reduced computation time. The Walsh Transform is used as a computational basis for evaluating a predistorter (PD) model. The mathematical properties of the Walsh theory are exploited to adapt a memory polynomial (MP) in the sequency domain. A block-based Walsh LMS is introduced to seek the optimal PD coefficients. Simulations and results of linearization of class-AB PAs are exhibited. The comparison with conventional DPD algorithms shows that the proposed method converges 10 times faster with a reduction of 12% of the complexity for similar accuracy. Finally, a complete DPD architecture based on the Walsh Transform is proposed.

The IEEE Solid-State Circuits Society (SSCS) Bordeaux University Student Branch Chapter (SBC) organized three events from November 2022 to March 2023.

With the need of maximizing the efficiency of Radio Frequency (RF) systems while respecting strict constraints in terms of EVM requirements, Power Amplifiers (PAs) predistortion appears as a way to improve circuits performances. Indeed, maximum efficiency is near the maximum output power that the PA can display. However, in this use area, PAs introduce distortion and phase variation. In this paper, a novel method for the linearization of RF Power Amplifiers is presented. The sequential transform is first used to evaluate a digital model of predistortion for the PA. A AB-Class PA is designed and is used in the proposed predistortion system to highlight the benefits of the overall architecture.

A wideband Power Amplifier (PA) with controlled efficiency based on the second harmonic matching and designed in 28nm FDSOI technology is proposed in this paper. The output network uses the harmonic processing techniques, especially the class-J one to control the Power Added Efficiency (PAE) over the Bandwidth (BW). The gain is between 16 and 19dB, $P_{sat}$ is between 18.5 and 20.9dBm and the PAE is 45% in the 3dB small signal BW from 2.4 to 5.1GHz. In this paper, we investigate the efficiency control principle.

This paper shows the design of a low-cost IoT device which provides data that are processed in order to estimate the number of people in a room and how they interacted distancially over a period of time ranging from the minute to the week. Our device is based on the collection of Bluetooth IDs as well as their RSSI signal strength. The data collected is sent to a server through a LoRa communication. The data collected is then processed with MATLAB to estimate contacts in-between people and verify the compliance with the maximum human capacity in a room. The device had to collected a set of data over one week of experiments. This paper first presents the steps that were followed to create a prototype to retrieve the Bluetooth IDs. Then, it presents simulations carried out with the Matlab software to estimate the distribution of people in an environment. And finally, the experimental results are presented and analyzed. The analysis of the simulation results concluded about a possible efficiency of our device to estimate the distancing interaction between people in a community as well as if they respected quotas of people allowed in a room. In addition, the experimental results are very encouraging.