The D-band is a promising candidate for high-speed, low-latency communication systems. However, power amplifier (PA) modeling at D-band frequencies is challenging due to technology diversity and significantly wider bandwidths compared to conventional narrowband systems. In this work, we propose a simplified Lookup Table-based Parallel Hammerstein (LUT-PH) model along with a corresponding evaluation methodology. The LUT-PH model is systematically compared with the Memory Polynomial (MP) model using an InP D-band PA as a case study. Results show that, under identical extraction and evaluation conditions, the MP model achieves higher modeling accuracy, while the LUT-PH model exhibits greater robustness under varying signal bandwidths and input backoff (IBO) levels. System-level simulations further reveal that bandwidth variations have limited impact when the IBO is selected close to the peak-to-average power ratio (PAPR) of the input signal, whereas their influence becomes more pronounced at higher IBO values. To the best of our knowledge, this is the first study to comprehensively discuss, compare, and integrate wideband memory models within a D-band system simulation.

Virtual reality (VR) systems demand high throughput to enable high-quality video transmission. In the 6 G subnetwork, the sub-THz is a potential candidate for the VR application. At those frequencies, the small wavelength of THz signals enables the realization of the integration of a larger number of antennas compared with mm-wave or low band frequency. How to optimize the power consumption for the access point (AP) and head-mounted displays (HMDs) in the sub-THz band has not yet been studied in the literature. In this paper, a simulation environment has been developed to assess the power consumption of VR communication systems by considering a sub-THz multi-user MIMO system along with a dedicated power model. An optimization problem is written to jointly optimize the average power consumption of the AP and HMD, or either AP or HMDs individually, while meeting the throughput and BER requirements. We explore the trade-off between the complexity of the AP and HMDs, offering insights into system-level design choices for various VR user experiences, considering different video resolutions, compression schemes, antenna configurations, and bandwidth settings. Additionally, we investigated computational offloading from the HMD to the AP, providing a potential energy-saving solution for batteryconstrained HMDs.

In the coming 6th Generation (6G) era, the perva-siveness of wireless communications in everyday life and vertical markets is expected to take a major leap, enabling revolutionary and highly demanding use cases. In-X subnetworks are expected to be located at the edge of the 6G 'network of networks'; they can provide short-range high-performance wireless connectivity in entities like robots, industrial production modules, vehicles, classrooms, etc., overcoming the limitation of current wireless technologies in terms of data rate, latency, complexity, and reliability. In this paper, we present the vision of the 6G SHort range extreme communication IN Entities (6G-SHINE) project, granted by the Smart Network and Services Joint Undertaking (SNS JU). 6G-SHINE is the first project exclusively focused on short-range in-X subnetworks, and aims at providing a significant breakthrough in multiple wireless communication fields, from physical layer to network architectures. We present the main project objectives and provide an overview of the technology components being researched. Also, we discuss the expected long-term beneficial impact of the project and its potential for future 6G standardization.

Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into the pipeline architecture and by using multi-core architectures. Two high rate medium size QC LDPC codes are designed with fast decoding convergence speed for this architecture. Both codes are implemented with single core and multi-core architectures to explore different trade-offs between code design, communication performance and implementation. The four decoders are implemented in 16 nm CMOS FinFET technology with a clock rate of 1 GHz. The placement and routing implementation results show that the single core decoder for the LDPC (1027, 856) code is able to provide 114 Gb/s throughput at maximum 3 iterations with an area of 0.173 mm(2) and energy efficiency of 1.56 pJ/bit; the multi-core decoder for the (1032, 860) code is able to provide 860 Gb/s throughput at maximum 2 iterations with an area of 1.48 mm(2) and energy efficiency of 3.24 pJ/bit. The multi-core decoder achieves the highest throughput in the literature for medium size (1-2k) LDPC codes. When compared with other state-of-the-art fully parallel high speed architectures, the proposed architectures bring a significant gain both in area efficiency and energy efficiency while keeping the ability to offer flexibility in code rate, number of iterations and early stop.

IEEE 802.11ay is the amendment to the 802.11 standard that enables Wi-Fi devices to achieve 100 Gbps using the unlicensed mm-Wave (60 GHz) band at comparable ranges to today’s commercial 60 GHz devices based on the 802.11ad standard. In this paper, we propose a full row-based layered LDPC decoder supporting all the coding rates for 802.11ay. Taking the property of the parity check matrix of 802.11ay, combining multiple layers into single layer improves the hardware utilization hence increases the throughput. The throughput is further increases by interleaving multiple frames to improve the utilization of each pipeline stage. The decoder is synthesized at both 28 nm and 16 nm CMOS technology and power estimated with stimuli at 7db and 3.5db. The 28 nm implementation running at 600 MHz and achieves a throughput of 67 Gbps for coding rate 13/16 at 4 iterations with area efficiency of 160 Gbps/sqmm and consumes an average power consumption of 408 mW and 141 mW, yielding energy efficiency of 6.05 pJ/bit and 2.1 pJ/bit at 3.5db and 7db. The 16 nm implementation running at 1 GHz and achieves a throughput of 112 Gbps at 4 iterations with area efficiency of 589 Gbps/sqmm and consumes an average power of 408mW and 163mW, yielding energy efficiency of 3.64 pJ/bit and 1.45 pJ/bit at 3.5db and 7db.

In this paper, we describe HW/SW cooptimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, tasklevel out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

Spin-torque transfer magnetic random access memory (STT-MRAM) has emerged as a promising nonvolatile memory technology, with advantages, such as scalability, speed, endurance, and power consumption. This paper presents an STT-MRAM cell operation channel model with write and read operations for information theorists and error correction code designers. This model considers the effects of process variations and thermal fluctuations and considers all principle flaws during the fabrication and operation processes. With this model, evaluations are not only made for the write channel, the read channel, but also the write and read channel with metrics, such as operation failure rate, bit error rate, channel ergodic capacity, and channel outage probability at certain outage capacity. Moreover, it is proved that the distributions of written-in bit states are not uniformly distributed and are proportional to their respective write success probabilities. Finally, simulation results show that practical code rates and code block lengths can guarantee reliable performances only if the operation success rate difference between state 1 and state 0 is small enough.

Lattice Reduction aided MIMO detectors have been demonstrated to offer a promising gain by providing near-optimal performance. This paper presents a C-programmable ASIP baseband processor, for near-optimal MIMO detection targeting a 4×4 LTE system. The detector supports multiple MIMO detection modes, with both hard and soft output. In order to improve implementation efficiency, the previously reported MIMO detection algorithm Multi-Tree Selective Spanning Detector (MTSS) is modified to use orthogonal real-valued decomposition (ORVD). Afterwards, a low-complexity log-likelihood-ratio (LLR) improvement technique called counter-ML bit-flipping algorithm is proposed. The proposed LLR generation algorithm has been designed to take advantage of MTSS, by maximizing the reuse of computations. Performance of the proposed solution can be tuned ranging from SIC to near-ML to near-MAP. The baseband processor is designed using 40 nm process technology with an equivalent gate-count (GE) of 68.41 kGE. Operating at 600 MHz for a 4×4 QAM-64 LTE system, the processor delivers peak-throughputs of 3.6 Gbps and 2.05 Gbps in case of hard and soft output MIMO detection, with 13.03 mW and 22.99 mW respective power consumption. The corresponding energy efficiency is 3.61 pJ/bit and 11.17 pJ/bit. In terms of energy efficiency, the proposed reconfigurable solution is comparable to recently reported ASIC MIMO detectors, while providing multiple-modes of operation and the flexilibility of C-programming.

Aggressive power supply voltage V (d d) scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical V (d d) results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal V (d d) condition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.

Rotated and cyclic-Q delayed (RCQD) quadrature amplitude modulation (QAM) improve DVB-T2 system performance over highly time-frequency selective channels. However, when compared with conventional QAM demapper, the RCQD demapper requires a higher computational complexity. In this paper, a complexity-reduced max-log demapper is derived and implemented over a FPGA platform. The proposed demapper allows to find the maximum likelihood (ML) point with a search spanning only √M signal constellation points and guarantees to obtain the same log-likelihood ratio (LLR) metrics as the optimum max-log soft decision demapper while spanning at most 2√M signal constellation points. The optimized hardware implementation introduces only a slight performance loss compared to the floating-point full complexity max-log performance.

This brief proposes a new compression technique of next-iteration initialization metrics for relaxing the storage demands of turbo decoders. The proposed scheme stores only the range of state metrics as well as two indexes of the maximum and minimum values, while the previous compression methods have to store all of the state metrics for initializing the following iteration. We also present a hardware-friendly recovery strategy, which can be implemented by simple multiplexing networks. Compared to the previous work, as a result, the proposed compression method reduces the required storage bits by 30% while providing the acceptable error-correcting performance in practice.

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency of 23.8 Gbps/mm2 for the ½ coding rate working at 18.4Gbps. With frequency, voltage scaling and multi-core management, the decoder supports a wide range of throughput, from 1.8Gbps to 18.4Gbps. The measurement results show the ASIP based design not only provides an energy efficient high speed solution but also be competitive with published ASIC solution at low and medium throughput scenarios.

The design of multi-Gbit/s low-density parity-check code (LDPC) decoders has become a hot topic in recent years to meet the growing demand of the transformation towards 4G. An area and energy efficient multi-Gbit/s LDPC decoder engine with a fully paralleled layered architecture based on an application-specific instruction set processor (ASIP) using Synopsys IP designer is presented. When the ASIP core is instantiated for 802.11ad, it achieved a throughput of up to 7 Gbit/s at three iterations with a latency of 95 ns, a record energy efficiency of 2.5 pJ/bit/iteration and an area efficiency of 54.5 Gbit/s/sq-m in CMOS 28 nm technology for the 1/2 rate, showing it to be competitive against published ASIC solutions.

Lattice Reduction aided softoutput MIMO detectors have been demonstrated to offer a promising gain. However, computing Log-Likelihood ratios (LLR) for near-optimal MIMO detection, still poses a significant challenge for practical implementations. In this work, we present counter-ML bit-flipping algorithm for LLR generation. The proposed LLR generation algorithm has been designed to take advantage of the previously reported list generation algorithm, Multi-Tree Selective Spanning (MTSS), by maximizing the reuse of computations. Afterwards, a C-programmable MIMO detector architecture providing both data level parallelism (DLP) and instruction level parallelism (ILP), is designed for implementation. The proposed solution supports multiple MIMO detection modes, with both hard and softoutput. Performance of the proposed solution can be tuned ranging from SIC to near-ML to near-MAP, by adjusting a single parameter. In case of 4 × 4 QAM-64, it achieves peak-throughputs of 2.43Gbps and 629Mbps in case of hard and softoutput MIMO detection, with only 66.37mW and 76.14mW respective power consumption.

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of the transformation towards 4G. In this paper, we describe an energy efficient multi-Gbps LDPC decoder engine based on ASIP using Target tool suite. The ASIP core can be configured as half-layer paralleled or quarter-layer paralleled decoding, which offers a good trade-off between the throughput and power/area efficiency when compared to the state-of-art fully paralleled ASIC based multi-Gbps LDPC decoder. When the ASIP core is instantiated for 802.11ad, it achieved a throughput up to 5.3 Gbps at 5 iterations with a latency of less than 150 ns and a record energy efficiency of 4.3 pJ/bit/iteration in 40G TSMC technology for the coding rate 13/16, showing to be competitive versus published ASIC solutions.

Multi-gigabit LDPC decoders are demanded by standards such as IEEE 802.11ad and IEEE 802.15.3c. In order to achieve high throughput, most published multi-gigabit designs use row-paralleled architecture. In this paper, we proposed a half-row paralleled LDPC decoder with half layer level pipeline and single permutation network for the 802.11ad standard, which reduces the hardware resources almost by half compared to the state-of-the-art row-paralleled LDPC decoder, achieving a good trade-off between energy efficiency and area efficiency. The decoder achieves a throughput of 5.6 Gbps and consumes only 99 mW for the highest coding rate 13/16 at 5 iterations, working at 500 MHz by using 40nm G technology, yielding an energy efficiency of 3.53 pJ/bit/iteration and area efficiency of 35 Gbps/sqmm.

Rotated QAM constellations improve Bit-Interleaved Coded Modulation (BICM) performance over fading channels. Indeed, an increased diversity is obtained by coupling a constellation rotation with interleaving between the real and imaginary components of transmitted symbols either in time or frequency domain. Iterative processing at the receiver side can provide additional improvement in performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. Scheduling an efficient message passing algorithm with low latency between the demapper and the LDPC decoder represents the main contribution. The design and the FPGA prototyping of the resultant shuffled iterative BICM receiver are then described. Architecture complexity and measured performance validate the potential of iterative receiver as a practical and competitive solution for the DVB-T2 standard.

Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously existing techniques. Iterative processing at the receiver side can provide additional improvement to the BICM performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. The main contribution is scheduling an efficient message passing algorithm with low latency between the demapper and the LDPC decoder. A BER performance comparison between a fixed-point version that considers architectural constraints and a theoretical version over a fading channel with erasure is presented. It validates the potential of iterative receiver as practical and competitive solution for the DVB-T2 standard.