Damage accumulation profiles induced by ion implantation into single-crystalline silicon layers and preamorphized silicon layers were investigated by the photoacoustic displacement (PAD) method. Boron ions were implanted at 10 keV with 1 x 10(15) ions/cm(2) and 3 x 10(15) ions/cm(2) into single-crystalline silicon and preamorphized silicon. Preamorphization was achieved by fluorine ion implantation prior to boron ion implantation. These implanted layers were annealed at 950 degrees C for 30 s by rapid thermal annealing. Damage profiles measured by PAD were compared to measured and calculated dopant and damage profiles. Effects of ion dose, annealing temperature, and combination of fluorine and boron implants were studied. Analysis of secondary ion mass spectroscopy profiles of fluorine combined with boron yielded values of 5.93 eV for F-B binding energy in a segregated region. (c) 2005 The Electrochemical Society.

Plasma immersion ion implantation (PIII) offers certain enabling advantages in several areas over a conventional beamline ion implanter: implant time independent of substrate size, lower costs, and higher dose rate. Silicon Genesis' novel Protonic Mode/sup TM/ technology achieves ion density exceeding 10/sup 12/ cm/sup -3/, H/sup +//H/sub 2//sup +/ ion mass purity ratio at greater than 100:1, and is cluster-tool compatible. At /spl les/5 kV implant potentials, SiGen's PIII achieves average currents in excess of 150 mA, with an estimated hydrogen ion current of >50 mA.

The desire for higher carrier mobilities for thin-channel CMOS, such as fully-depleted SOI, has focused attention on the behavior of dopants in Si1-xGex materials. In this work, the diffusion of boron implanted at 0.5 keV was studied for 5 see anneals between 800 to 1050 degreesC for silicon (Cz and epitaxial) and Si1-xGex layers with Ge content of 7 and 25%. The implant dose of boron ions was 5x10(14) ions/cm(2). The epi-siticon and Si1-xGex layers were similar to200 nm thick so that the entire diffused profile was within the epitaxial layers. Strongly increased diffusion, compared to Cz- and epi-silicon, was found for boron atoms in layers with the Ge content of 7% and 25% for anneal temperatures above 900 degreesC.

Charging characteristics of As/sup +/, BF/sub 2//sup +/, and B/sup +/ high-current ion implants, performed at different energies and different plasma flood system settings, were measured using bare and resist-covered CHARM/spl reg/-2 wafers patterned with a six-field mask containing holes ranging from 2 /spl mu/m to 0.5 /spl mu/m (clear and resist-covered fields were also used). The results show significant differences in the charging characteristics of high-current ion implanters compared to contemporary plasma-based process tools. The differences appear to be independent of ion energy, but depend on the set-up conditions of the plasma flood system used to limit positive charging caused by the ion beam. In contrast to plasma tools, the implants typically exhibited positive and negative potentials independent of hole size. The positive and negative current densities measured in the resist holes were also independent of hole size (and significantly higher than in the clear field). However, a 500 eV B/sup +/ implant with modern plasma flood control produced positive and negative potentials that scaled with hole size, as expected for electron shading, but with current densities below CHARM/spl reg/-2 detection levels. This establishes an existence proof that optimal plasma flood can achieve near perfect current balance between the positive charging from the ion beam and the negative charging from the flood plasma. Altogether, these results suggest that charging damage in high-current ion implanters should be controllable when implant mask and device features are scaled down.

Results for epi-based final surface finishing are reported for ultra-thin (<50 nm device layers) SOI wafers. Near and sub-Angstrom surface roughness over lateral scales up to 10 /spl mu/m and device layer thickness uniformity range (max-min) of 10% have been achieved for 200 and 300 mm SOI wafers.

A plasma immersion ion implantation (PIII) system is described which provides the capability to bridge the range between research exploration and commercial applications for materials modification of electronic materials, with a particular focus on layer transfer processes. The Silicon Genesis PIII system is capable of operation at high plasma densities (≈5×1011 ions/cm3 at the wafer) with high purity, mono-species ionization (>99% H+ ions with a hydrogen plasma). The first generation of Silicon Genesis PIII systems is equipped to use 200-mm wafers (through an automated loadlock) and pulsed potentials up to 50 kV. Use of the mono-species ionization characteristic of the Silicon Genesis PIII system provides the capability to precisely vary the characteristics of surface layers through implantation of atoms and damage creation at well-controlled depths in the materials of choice. The Silicon Genesis PIII system is designed for efficient production of SOI and other layer transfer-generated materials and can be adapted for materials modification of more complex structures and work pieces.

A novel process has been developed for fabrication of SOI wafers by layer transfer techniques which results in an as-cleaved Si surface finish with an RMS roughness of the order 1-2 Angstrom. The Si film thickness uniformity is routinely better than 2% for 100 to 200 nm layers on 200 mm wafers. Because the bonding and cleaving steps in the layer transfer process are done at room temperature, the process is easily controlled and accomplished with high-productivity methods.

Planar CMOS transistors on bulk silicon wafers are expected to reach their limits at gate sizes about 50nm in 2005-06. Many of the process and materials constraints that combine to force this change in technology path are relaxed or removed for CMOS devices fabricated on SOI wafers. This article outlines the principal issues limiting junction formation for sub-100nm CMOS on bulk silicon and presents an alternative roadmap using SOI wafers. An SOI wafer fabrication technology is described that provides a room temperature, atomic layer cleaving process with unprecedented levels of control on silicon layer thickness, as well as a clear path for extension towards the ultrathin SOI regime.

Charge control during ion implantation depends on the interaction of the ion beam plasma with the device wafer and other local sources of charged species. The key role of the net ion density, plasma electron temperature and plasma ion mass are discussed. The value of local monitoring of the current-voltage characteristics of the net plasma at the wafer surface with EEPROM sense and measurement devices is illustrated with effects of various charge control systems and the influence of resist patterning on the net current flow to the wafer. The special challenges of space charge control for sub-keV ion beams and the impact on local doping uniformity are also discussed

Boron ion implantation into pre-amorphized silicon is studied. Pre-amorphization is performed either by F+ or Si+ implantation prior to B+ implantation at 10keV with 3×1015ions/cm2. Broadening of the boron profile can be suppressed markedly in the pre-amorphized layers. For instance, the as-implanted depth at a B concentration of 1×1018atoms/cm3 decreases from 0.19 to 0.1μm for implantation into a pre-amorphized layer compared to B implantation into crystalline silicon. After annealing at 950°C, B atoms diffuse much more rapidly in the pre-amorphized layers than in the crystalline silicon case. Nevertheless, shallower junctions are obtained with the use of pre-amorphization. For dual F+ and B+ implantation at F+ doses above 1×1015 F+/cm2, fluorine is found to segregate to the peak of the boron profile during annealing. Fluorine is also trapped at the peak of the as-implanted fluorine profile peak and near the amorphous–crystalline interface. The effects of fluorine dose and anneal temperature on the F precipitation are described and compared to results for BF+2 implants.

Doping requirements for ULSI CMOS transistors are discussed as well as effects that influence doping accuracy and junction location, minimum practical junction depths, the impact of epi or CZ wafers on transistor doping process, elemental contamination and the yield impact of small particles on low-energy implanted junctions. Various doping technologies; beamline implantation, plasma immersion, cluster-ion beams, gas immersion laser doping, CVD/RTP and MBE techniques, are benchmarked.

Wafer charging effects in an Applied Materials 9500 implanter were studied for high current As and BF2 implants with EEPROM-based sense and measurement devices (CHARM(R)-2) and transistor structures (SPIDER). The operational modes of the implanter were deliberately driven non-optimal states in order 60 test the sensitivity of the wafer-level monitors. Good correlation was found between data from the CHARM and SPIDER monitors as well as from machine-based indicators, such as the wheel current. A broad and stable operating window was seen for operation under normal conditions

Plasma Flood System (PFS) was developed for the Precision Implant 9500 to achieve the most advanced charging control on wafer surface for high throughput implant processes over a wide range of beam current. A novel configuration of plasma discharge chamber made it possible to generate primary electrons at between 0 eV and 5 eV while maintaining a high emission current of over 100 mA. Space charge limit in generating low energy electrons was overcome by combining the arc discharge chamber at the anode potential with a negatively biased confinement tube via a potential shielding. Magnetic field from the plasma source coupled with a filament induced field plays an important role in transporting low energy electrons out of the chamber. The system also has a feature to increase the emission by one order of magnitude by offsetting a reference potential of the plasma source. This paper discusses the physics of the PFS describing how the electrons are generated at below 5 eV and transported at a high flux into the guide tube held typically at -10 V.

With the development of quantitive measures of current-voltage characteristics (CHARM(R)-2) and a beam-plasma model for charge flows to and from the wafer surface, a more comprehensive view of wafer charging has emerged. A beam-plasma model has been developed which describes both positive and negative current-voltage characteristics of the beam plasma. A quantitative description has been achieved for a variety of charge control systems; including dense and dilute plasma flows, electron showers as well as for photoresist outgassing effects.

Wafer charging effects in an Applied Materials 9500 implanter were studied for As implants with EEPROM-based sense and measurement devices and capacitors with either large oxide areas or large oxide-poly area ratios. The operation of the Plasma Flow Source; arc discharge current, guide tube voltage and confinement magnets, were varied to study the effects on these various charge monitors. The large-area oxide capacitors responded to conditions that increased the negative charge flows to the wafers. The large-area antenna contains structures responding to conditions that produced positive current flows

A complete set of doping profiles for a SEMATECH 0.25 /spl mu/m CMOS/DRAM model process were implanted into 200 mm wafers with a 9500/spl times/R implanter. The implants ranged in energy from 10 to 600 keV over a dose range from 7/spl times/10/sup 11/ to 3/spl times/10/sup 15/ ions/cm/sup 2/. The profiles were analyzed with an array of SIMS and SRP and junction staining techniques. Both as-implanted and annealed profiles were measured.

The transition from electronic to nuclear stopping power mechanisms for < 10 keV B in Si has resulted in a new class of damage accumulation effects. Strong correlations are seen between beam current, wafer temperature during implant, anneal conditions and the damage accumulation, diffusion and activation for low-energy B implants. In response to these challenges, new characterization methods and processes are being explored; such as the use of multi-species implantation and depth profiling of damage distributions with photo-acoustic probes.

Modeling of ULSI ion implantation processing poses a complex set of challenges for efficient description of physical processes. Accuracy requirements for range and damage profiles and the need for advances in modeling of defect-enhanced diffusion and dopant activation of Si are rapidly increasing. The overriding requirement is the need to incorporate accurate physical models into efficient descriptions of 3-dimensional device structures.

Contamination associated with ion implantation is discussed with an emphasis on secondary ion mass spectrometry (SIMS) characterization. This article is organized according to the path of the ion beam through an ion implanter, starting with the source and continuing to the end station. Specific examples are provided using SIMS as a tool to detect and resolve contamination problems.

The mechanism responsible for charging damage to integrated circuit device insulators is treated as a plasma phenomenon, in which the beam/plasma drives potential differences on the process surface. J−V data obtained with the CHARM2 diagnostic in a high current implanter (flood OFF) are fit with a plasma probe model. The fit indicates plasma buildup over the wafer surface. A cold plasma flood is suggested as a means of limiting potential differences during ion implantation.