Circuits implementing the concept of Selective Fault Tolerance according to [1] are fault-tolerant for a specified subset of inputs. In this paper, a new heuristic is presented to make the method of Selective Fault Tolerance applicable to industrial designs. The heuristic can be efficiently implemented by use of conventional design tools. Compared to TMR, the method, in combination with the heuristic, saves a huge amount of area redundancy and fault tolerance is adapted to the real requirements of a system specification. This is demonstrated by experimental results obtained from circuit descriptions in Verilog and a synthesis with the tool Synopsys.

This paper introduces the concept of Selective Fault Tolerance for sequential circuits. A sequential circuit that is designed according to this method is fault-tolerant for an arbitrarily selected subset of input sequences that are applied in one or more arbitrarily specified states. Once a selected input sequence is applied in a specified state, the circuit guarantees the same degree of fault tolerance as Triple Modular Redundancy (TMR). No fault tolerance is guaranteed in any other case. A simple heuristic algorithm for the design of such circuits is presented and for a benchmark circuit the reduction of area overhead compared to TMR is experimentally determined. The proposed method is a generalization of Selective Fault Tolerance for combinational circuits as described in [1].

This paper presents a new method of fault-tolerant design for combinational circuits. For an arbitrary chosen subset X 1 of inputs the designed system is fault-tolerant, but not necessarily for the other inputs. For all the inputs from X 1 the same level of fault tolerance as for Triple Modular Redundancy (TMR) is achieved. Compared to TMR the necessary area can be significantly reduced. Since the subset X 1 of inputs, for which the system is fault-tolerant, can be chosen by the designer, the proposed fault-tolerant design method is optimally adapted to the real requirements of fault tolerance.

This paper presents a new on-line checking scheme for asynchronous handshake protocols. The proposed scheme requires very small chip area while maintaining high coverage for all considered faults which are briefly exposed. In addition to simple pass-fail information the checker provides off-line diagnosis capabilities in order to further analyze the cause of a fault and the time of its occurrence. In order to verify its functionality the checker was proven by performing analogue simulations. In addition the area overhead and the power consumption was determined and compared with existing implementations.