Plants are a vital component of human life on Earth; they provide us with food and essential nutrients as well as the oxygen we breathe. However, the science education community struggles to find ways to make plant processes less abstract and more understandable for learners. In this article we demonstrate how we make plant processes more understandable for learners by observing the behaviors of a specific plant structure, a stoma, which is a microscopic opening that plays a role in the movement of matter into and out of a plant. Recent research across plant-related science fields centers on plant stomata because they protect plants from various environmental strains, including attacks from pathogens. Translating this research into science classroom instruction has not occurred extensively. A key impediment is that few common methods to make stomata visible or demonstrate their dynamic nature to learners are available. The activities we share here make stomata visible utilizing a specific plant, Tradescantia zebrina, and common laboratory equipment. In the first activity, we share how to demonstrate stomata closing and opening by manipulating a combination of these environmental factors. In the second activity, we describe how to create a visual simulation of stomata response to attacks from microorganisms.

As a plant hormone, salicylic acid (SA) plays essential roles in plant defense against biotrophic and hemibiotrophic pathogens. Significant progress has been made in understanding the SA biosynthesis pathways and SA-mediated defense signaling networks in the past two decades. Plant defense responses involve rapid and massive transcriptional reprogramming upon the recognition of pathogens. Plant transcription factors and their co-regulators are critical players in establishing a transcription regulatory network and boosting plant immunity. A multitude of transcription factors and epigenetic regulators have been discovered, and their roles in SA-mediated defense responses have been reported. However, our understanding of plant transcriptional networks is still limited. As such, novel genomic tools and bioinformatic techniques will be necessary if we are to fully understand the mechanisms behind plant immunity. Here, we discuss current knowledge, provide an update on the SA biosynthesis pathway, and describe the transcriptional and epigenetic regulation of SA-mediated plant immune responses.

As a plant hormone, salicylic acid (SA) plays essential roles in plant defense against biotrophic and hemibiotrophic pathogens. Significant progress has been made in understanding the SA biosynthesis pathways and SA-mediated defense signaling networks in the past two decades. Plant defense responses involve rapid and massive transcriptional reprogramming upon the recognition of pathogens. Plant transcription factors and their co-regulators are critical players in establishing a transcription regulatory network and boosting plant immunity. A multitude of transcription factors and epigenetic regulators have been discovered, and their roles in SA-mediated defense responses have been reported. However, our understanding of plant transcriptional networks is still limited. As such, novel genomic tools and bioinformatic techniques will be necessary if we are to fully understand the mechanisms behind plant immunity. Here, we discuss current knowledge, provide an update on the SA biosynthesis pathway, and describe the transcriptional and epigenetic regulation of SA-mediated plant immune responses.

Salicylic acid(SA) or 2-hydroxybenzoic acid,better known as the active ingredient in aspirin,is a phenolic plant hormone that plays an essential role in plant defense against biotrophic and semi-biotrophic pathogens(Fu and Dong,2013).

Plant resistance proteins play a key role in detecting pathogen infection and activating plant defense. Two recent papers by Horsefield et al. and Wan et al. revealed that the TIR domain in resistance (R) proteins functions as an NAD+-cleaving enzyme. This enzymatic activity is induced by pathogen recognition and is indispensable for the R protein-dependent cell death response.

In high performance computing (HPC) applications, the speed of the L1 cache will typically determine the maximum frequency (/Max) of the processor core. Companies that mass produce high-performance microprocessors commonly have the L1 cache consist of fully-custom macros: to ensure that the performance of the L1 cache does not limit the f MAX or throughput of the processor. In addition, it is also common for the custom L1 cache designs to use a two-port 8T or a large 6T bitcell, along with domino read logic and very short BL [2,3]. These designs tradeoff density and area for high performance. This paper presents a different approach, one which can satisfy a range of different applications; a memory compiler that can generate more than 10,000 different high-speed L1 cache macro configurations is proposed. The 7nm L1-cache compiler described in this paper uses a high-current (HC) 6T bitcell, which is more area efficient than an 8T bitcell. The HC bitcell, along with small-signal sensing, allows for long BL (256b), leading to further area efficiency improvements. Since these L1 macros are just as likely to be used in mobile applications as they are to be used in HPC applications, they were implemented using the array dual-rail (ADR) architecture [4]. The ADR architecture (Fig. 11.3.1) allows the periphery circuits of the L1 macro to operate at the same voltage as the processor core: a lower l/ DD results in dynamic power savings. ADR performance is also improved, over an interface dual-rail, when the SRAM and logic supplies are equivalent, as ADR design does not suffer from a level-shifter delays on the inputs or outputs.

Mobile applications, such as smartphones streaming HD videos or virtual-reality headsets rendering 3D landscapes, need SRAM memories that can be put in a low-power state to extend battery life, but can also offer high performance operation when required [1]. This paper will merge a 10nm technology with a dual-rail SRAM architecture to achieve superior power savings and performance scaling in comparison to the previous 16nm technology node [2]. Due to its simple design and area efficient layout, the 6T SRAM bitcell continues to be the primary memory technology used in almost all SoC and processor designs in high volume manufacturing today. The 10nm technology uses low-leakage, high-performance, second-generation FinFET transistors; it also offers a 6T cell (0.042µm2), for area and power savings, that does not require read or write assist circuits to achieve low voltage (Vmin) operation. This bitcell uses a fin ratio of 1∶2∶2 (PU:PG:PD), as illustrated in Fig. 12.3.1.

This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.

Lists the sessions held at the conference proceedings.

We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage IC's with “instant-on” capability are ideal.